mirror of
https://github.com/AsahiLinux/u-boot
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e6f48aad15
This adds support for i.MX6UL/ULL-based evaluation kits with SoMs by Kontron Electronics GmbH. Currently there are the following SoM flavors (SoM-Line): * N6310: SOM with i.MX6UL-2, 256MB RAM, 256MB SPI NAND * N6311: SOM with i.MX6UL-2, 512MB RAM, 512MB SPI NAND * N6411: SOM with i.MX6ULL, 512MB RAM, 512MB SPI NAND And the according evaluation boards (Board-Line): * N6310-S: Baseboard with SOM N6310, eMMC, display (optional), ... * N6311-S: Baseboard with SOM N6311, eMMC, display (optional), ... * N6411-S: Baseboard with SOM N6411, eMMC, display (optional), ... Currently U-Boot describes i.MX6UL and i.MX6ULL through separate config options at compile-time. Though the differences are so minor, that for the scope of these SoMs we just use a single defconfig that is compatible with both SoCs. Signed-off-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
124 lines
2.7 KiB
Text
124 lines
2.7 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2017 exceet electronics GmbH
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* Copyright (C) 2018 Kontron Electronics GmbH
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* Copyright (c) 2019 Krzysztof Kozlowski <krzk@kernel.org>
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*/
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#include <dt-bindings/gpio/gpio.h>
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/ {
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chosen {
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stdout-path = &uart4;
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};
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memory@80000000 {
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reg = <0x80000000 0x10000000>;
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device_type = "memory";
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};
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};
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&ecspi2 {
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cs-gpios = <&gpio4 22 GPIO_ACTIVE_HIGH>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ecspi2>;
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status = "okay";
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spi-flash@0 {
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compatible = "mxicy,mx25v8035f", "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <0>;
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1 &pinctrl_enet1_mdio>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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micrel,led-mode = <0>;
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clocks = <&clks IMX6UL_CLK_ENET_REF>;
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clock-names = "rmii-ref";
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};
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};
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};
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&fec2 {
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phy-mode = "rmii";
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status = "disabled";
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};
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&qspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_qspi>;
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spi-nand";
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spi-max-frequency = <104000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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reg = <0>;
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reset_out>;
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pinctrl_ecspi2: ecspi2grp {
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fsl,pins = <
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MX6UL_PAD_CSI_DATA03__ECSPI2_MISO 0x100b1
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MX6UL_PAD_CSI_DATA02__ECSPI2_MOSI 0x100b1
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MX6UL_PAD_CSI_DATA00__ECSPI2_SCLK 0x100b1
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MX6UL_PAD_CSI_DATA01__GPIO4_IO22 0x100b1
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b009
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>;
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};
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pinctrl_enet1_mdio: enet1mdiogrp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
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>;
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};
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pinctrl_qspi: qspigrp {
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fsl,pins = <
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MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
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MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
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MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
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MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
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MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
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MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
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>;
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};
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pinctrl_reset_out: rstoutgrp {
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
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>;
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};
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};
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