mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-05 20:54:31 +00:00
30b1ecd265
CONFIG_BOARD_EARLY_INIT_F literally indicates board-specific codes and should be not 'default y' for all x86 boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
62 lines
1.4 KiB
C
62 lines
1.4 KiB
C
/*
|
|
* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/device.h>
|
|
#include <asm/arch/quark.h>
|
|
|
|
/*
|
|
* Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin.
|
|
*
|
|
* We cannot use any public GPIO APIs in <asm-generic/gpio.h> to control this
|
|
* pin, as these APIs will eventually call into gpio_ich6_ofdata_to_platdata()
|
|
* in the Intel ICH6 GPIO driver where it calls PCI configuration space access
|
|
* APIs which will trigger PCI enumeration process.
|
|
*
|
|
* Check <asm/arch-quark/quark.h> for more details.
|
|
*/
|
|
void board_assert_perst(void)
|
|
{
|
|
u32 base, port, val;
|
|
|
|
/* retrieve the GPIO IO base */
|
|
qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
|
|
base = (base & 0xffff) & ~0x7f;
|
|
|
|
/* enable the pin */
|
|
port = base + 0x20;
|
|
val = inl(port);
|
|
val |= (1 << 0);
|
|
outl(val, port);
|
|
|
|
/* configure the pin as output */
|
|
port = base + 0x24;
|
|
val = inl(port);
|
|
val &= ~(1 << 0);
|
|
outl(val, port);
|
|
|
|
/* pull it down (assert) */
|
|
port = base + 0x28;
|
|
val = inl(port);
|
|
val &= ~(1 << 0);
|
|
outl(val, port);
|
|
}
|
|
|
|
void board_deassert_perst(void)
|
|
{
|
|
u32 base, port, val;
|
|
|
|
/* retrieve the GPIO IO base */
|
|
qrk_pci_read_config_dword(QUARK_LEGACY_BRIDGE, LB_GBA, &base);
|
|
base = (base & 0xffff) & ~0x7f;
|
|
|
|
/* pull it up (de-assert) */
|
|
port = base + 0x28;
|
|
val = inl(port);
|
|
val |= (1 << 0);
|
|
outl(val, port);
|
|
}
|