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NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
83 lines
3.1 KiB
C
83 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2017-2018 NXP
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* Copyright 2014-2015, Freescale Semiconductor
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*/
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#ifndef _FSL_LAYERSCAPE_CPU_H
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#define _FSL_LAYERSCAPE_CPU_H
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#ifdef CONFIG_FSL_LSCH3
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#define CONFIG_SYS_FSL_CCSR_BASE 0x00000000
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#define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000
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#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000
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#define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000
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#ifndef CONFIG_NXP_LSCH3_2
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#define CONFIG_SYS_FSL_IFC_BASE1 0x30000000
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#define CONFIG_SYS_FSL_IFC_SIZE1 0x10000000
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#define CONFIG_SYS_FSL_IFC_SIZE1_1 0x400000
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#endif
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#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
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#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
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#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000
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#define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000
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#ifndef CONFIG_NXP_LSCH3_2
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#define CONFIG_SYS_FSL_IFC_BASE2 0x500000000
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#define CONFIG_SYS_FSL_IFC_SIZE2 0x100000000
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#endif
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#define CONFIG_SYS_FSL_DCSR_BASE 0x700000000
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#define CONFIG_SYS_FSL_DCSR_SIZE 0x40000000
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#define CONFIG_SYS_FSL_MC_BASE 0x80c000000
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#define CONFIG_SYS_FSL_MC_SIZE 0x4000000
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#define CONFIG_SYS_FSL_NI_BASE 0x810000000
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#define CONFIG_SYS_FSL_NI_SIZE 0x8000000
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#define CONFIG_SYS_FSL_QBMAN_BASE 0x818000000
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#define CONFIG_SYS_FSL_QBMAN_SIZE 0x8000000
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#define CONFIG_SYS_FSL_QBMAN_SIZE_1 0x4000000
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#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x200000000
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#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x200000000
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#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x200000000
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#define CONFIG_SYS_PCIE4_PHYS_SIZE 0x200000000
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#define CONFIG_SYS_FSL_WRIOP1_BASE 0x4300000000
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#define CONFIG_SYS_FSL_WRIOP1_SIZE 0x100000000
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#define CONFIG_SYS_FSL_AIOP1_BASE 0x4b00000000
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#define CONFIG_SYS_FSL_AIOP1_SIZE 0x100000000
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#define CONFIG_SYS_FSL_PEBUF_BASE 0x4c00000000
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#define CONFIG_SYS_FSL_PEBUF_SIZE 0x400000000
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#ifdef CONFIG_NXP_LSCH3_2
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#define CONFIG_SYS_FSL_DRAM_BASE2 0x2080000000
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#define CONFIG_SYS_FSL_DRAM_SIZE2 0x1F80000000
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#define CONFIG_SYS_FSL_DRAM_BASE3 0x6000000000
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#define CONFIG_SYS_FSL_DRAM_SIZE3 0x2000000000
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#else
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#define CONFIG_SYS_FSL_DRAM_BASE2 0x8080000000
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#define CONFIG_SYS_FSL_DRAM_SIZE2 0x7F80000000
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#endif
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#elif defined(CONFIG_FSL_LSCH2)
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#define CONFIG_SYS_FSL_BOOTROM_BASE 0x0
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#define CONFIG_SYS_FSL_BOOTROM_SIZE 0x1000000
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#define CONFIG_SYS_FSL_CCSR_BASE 0x1000000
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#define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000
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#define CONFIG_SYS_FSL_DCSR_BASE 0x20000000
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#define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000
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#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000
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#define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000
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#define CONFIG_SYS_FSL_IFC_BASE 0x60000000
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#define CONFIG_SYS_FSL_IFC_SIZE 0x20000000
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#define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000
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#define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000
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#define CONFIG_SYS_FSL_QBMAN_BASE 0x500000000
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#define CONFIG_SYS_FSL_QBMAN_SIZE 0x10000000
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#define CONFIG_SYS_FSL_DRAM_BASE2 0x880000000
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#define CONFIG_SYS_FSL_DRAM_SIZE2 0x780000000 /* 30GB */
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#define CONFIG_SYS_PCIE1_PHYS_SIZE 0x800000000
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#define CONFIG_SYS_PCIE2_PHYS_SIZE 0x800000000
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#define CONFIG_SYS_PCIE3_PHYS_SIZE 0x800000000
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#define CONFIG_SYS_FSL_DRAM_BASE3 0x8800000000
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#define CONFIG_SYS_FSL_DRAM_SIZE3 0x7800000000 /* 480GB */
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#endif
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int fsl_qoriq_core_to_cluster(unsigned int core);
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u32 cpu_mask(void);
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#endif /* _FSL_LAYERSCAPE_CPU_H */
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