Sean Anderson e5ca9a7523 riscv: Rework Sifive CLINT as UCLASS_TIMER driver ... This converts the clint driver from the riscv-specific interface to be a DM-based UCLASS_TIMER driver. In addition, the SiFive DDR driver previously implicitly depended on the CLINT to select REGMAP. Unlike Andes's PLMT/PLIC (which AFAIK never have anything pass it a dtb), the SiFive CLINT is part of the device tree passed in by qemu. This device tree doesn't have a clocks or clock-frequency property on clint, so we need to fall back on the timebase-frequency property. Perhaps in the future we can get a clock-frequency property added to the qemu dtb. Unlike with the Andes PLMT, the Sifive CLINT is also an IPI controller. RISCV_SYSCON_CLINT is retained for this purpose. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Pragnesh Patel <pragnesh.patel@openfive.com>		2020-09-30 08:54:46 +08:00
..
cpu	riscv: Rework riscv timer driver to only support S-mode	2020-09-30 08:54:45 +08:00
dts	fu540: dtsi: add reset producer and consumer entries	2020-08-04 09:19:41 +08:00
include/asm	riscv: Rework Andes PLMT as a UCLASS_TIMER driver	2020-09-30 08:54:45 +08:00
lib	riscv: Rework Sifive CLINT as UCLASS_TIMER driver	2020-09-30 08:54:46 +08:00
config.mk	kconfig / kbuild: Re-sync with Linux 4.19	2020-04-10 11:18:32 -04:00
Kconfig	riscv: Rework Sifive CLINT as UCLASS_TIMER driver	2020-09-30 08:54:46 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00