mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-08 22:24:32 +00:00
cd71b1d5d2
Add initial support for the Ingenic JZ47xx MIPS SoC. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
164 lines
3.1 KiB
Text
164 lines
3.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
|
|
|
|
#include <dt-bindings/clock/jz4780-cgu.h>
|
|
|
|
/ {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "ingenic,jz4780";
|
|
|
|
cpuintc: interrupt-controller {
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupt-controller;
|
|
compatible = "mti,cpu-interrupt-controller";
|
|
};
|
|
|
|
intc: interrupt-controller@10001000 {
|
|
compatible = "ingenic,jz4780-intc";
|
|
reg = <0x10001000 0x50>;
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <1>;
|
|
|
|
interrupt-parent = <&cpuintc>;
|
|
interrupts = <2>;
|
|
};
|
|
|
|
ext: ext {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
};
|
|
|
|
rtc: rtc {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
cgu: jz4780-cgu@10000000 {
|
|
compatible = "ingenic,jz4780-cgu";
|
|
reg = <0x10000000 0x100>;
|
|
|
|
clocks = <&ext>, <&rtc>;
|
|
clock-names = "ext", "rtc";
|
|
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
mmc0: mmc@13450000 {
|
|
compatible = "ingenic,jz4780-mmc";
|
|
reg = <0x13450000 0x1000>;
|
|
|
|
status = "disabled";
|
|
|
|
clocks = <&cgu JZ4780_CLK_MSC0>;
|
|
clock-names = "mmc";
|
|
};
|
|
|
|
mmc1: mmc@13460000 {
|
|
compatible = "ingenic,jz4780-mmc";
|
|
reg = <0x13460000 0x1000>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_MSC1>;
|
|
clock-names = "mmc";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart0: serial@10030000 {
|
|
compatible = "ingenic,jz4780-uart";
|
|
reg = <0x10030000 0x100>;
|
|
reg-shift = <2>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <51>;
|
|
|
|
clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
|
|
clock-names = "baud", "module";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart1: serial@10031000 {
|
|
compatible = "ingenic,jz4780-uart";
|
|
reg = <0x10031000 0x100>;
|
|
reg-shift = <2>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <50>;
|
|
|
|
clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
|
|
clock-names = "baud", "module";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@10032000 {
|
|
compatible = "ingenic,jz4780-uart";
|
|
reg = <0x10032000 0x100>;
|
|
reg-shift = <2>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <49>;
|
|
|
|
clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
|
|
clock-names = "baud", "module";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@10033000 {
|
|
compatible = "ingenic,jz4780-uart";
|
|
reg = <0x10033000 0x100>;
|
|
reg-shift = <2>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <48>;
|
|
|
|
clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
|
|
clock-names = "baud", "module";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@10034000 {
|
|
compatible = "ingenic,jz4780-uart";
|
|
reg = <0x10034000 0x100>;
|
|
reg-shift = <2>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <34>;
|
|
|
|
clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
|
|
clock-names = "baud", "module";
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
nemc: nemc@13410000 {
|
|
compatible = "ingenic,jz4780-nemc";
|
|
reg = <0x13410000 0x10000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges = <1 0 0x1b000000 0x1000000
|
|
2 0 0x1a000000 0x1000000
|
|
3 0 0x19000000 0x1000000
|
|
4 0 0x18000000 0x1000000
|
|
5 0 0x17000000 0x1000000
|
|
6 0 0x16000000 0x1000000>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_NEMC>;
|
|
|
|
status = "disabled";
|
|
};
|
|
|
|
bch: bch@134d0000 {
|
|
compatible = "ingenic,jz4780-bch";
|
|
reg = <0x134d0000 0x10000>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_BCH>;
|
|
|
|
status = "disabled";
|
|
};
|
|
};
|