mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-29 16:10:58 +00:00
caf7092294
Some chips provide their sysreset function in reset controller, which is normally a bit written to 1 to perform the sysreset. This patch adds a new sysreset driver to take advantage of it. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
21 lines
960 B
Makefile
21 lines
960 B
Makefile
# SPDX-License-Identifier: GPL-2.0+
|
|
#
|
|
# (C) Copyright 2016 Cadence Design Systems Inc.
|
|
|
|
obj-$(CONFIG_$(SPL_TPL_)SYSRESET) += sysreset-uclass.o
|
|
obj-$(CONFIG_ARCH_ASPEED) += sysreset_ast.o
|
|
obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
|
|
obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
|
|
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
|
|
obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
|
|
obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
|
|
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
|
|
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
|
|
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
|
|
obj-$(CONFIG_SYSRESET_SOCFPGA_S10) += sysreset_socfpga_s10.o
|
|
obj-$(CONFIG_SYSRESET_TI_SCI) += sysreset-ti-sci.o
|
|
obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
|
|
obj-$(CONFIG_SYSRESET_WATCHDOG) += sysreset_watchdog.o
|
|
obj-$(CONFIG_SYSRESET_RESETCTL) += sysreset_resetctl.o
|
|
obj-$(CONFIG_$(SPL_TPL_)SYSRESET_X86) += sysreset_x86.o
|
|
obj-$(CONFIG_TARGET_XTFPGA) += sysreset_xtfpga.o
|