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7831419d7b
DRA752 uses DDR3. Populating the corresponding structures with DDR3 data. Writing into MA registers if only MA is present in that soc. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: R Sricharan <r.sricharan@ti.com> Reviewed-by: Tom Rini <trini@ti.com>
428 lines
11 KiB
C
428 lines
11 KiB
C
/*
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* Timing and Organization details of the ddr device parts used in OMAP5
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* EVM
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*
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* (C) Copyright 2010
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* Texas Instruments, <www.ti.com>
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*
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* Aneesh V <aneesh@ti.com>
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* Sricharan R <r.sricharan@ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/emif.h>
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#include <asm/arch/sys_proto.h>
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/*
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* This file provides details of the LPDDR2 SDRAM parts used on OMAP5
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* EVM. Since the parts used and geometry are identical for
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* evm for a given OMAP5 revision, this information is kept
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* here instead of being in board directory. However the key functions
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* exported are weakly linked so that they can be over-ridden in the board
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* directory if there is a OMAP5 board in the future that uses a different
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* memory device or geometry.
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*
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* For any new board with different memory devices over-ride one or more
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* of the following functions as per the CONFIG flags you intend to enable:
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* - emif_get_reg_dump()
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* - emif_get_dmm_regs()
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* - emif_get_device_details()
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* - emif_get_device_timings()
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*/
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#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
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const struct emif_regs emif_regs_532_mhz_2cs = {
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.sdram_config_init = 0x80800EBA,
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.sdram_config = 0x808022BA,
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.ref_ctrl = 0x0000081A,
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.sdram_tim1 = 0x772F6873,
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.sdram_tim2 = 0x304a129a,
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.sdram_tim3 = 0x02f7e45f,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x000b3215,
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.temp_alert_config = 0x08000a05,
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.emif_ddr_phy_ctlr_1_init = 0x0E28420d,
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.emif_ddr_phy_ctlr_1 = 0x0E28420d,
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.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
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.emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
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.emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
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.emif_ddr_ext_phy_ctrl_5 = 0x04010040
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};
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const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
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.sdram_config_init = 0x80800EBA,
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.sdram_config = 0x808022BA,
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.ref_ctrl = 0x0000081A,
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.sdram_tim1 = 0x772F6873,
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.sdram_tim2 = 0x304a129a,
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.sdram_tim3 = 0x02f7e45f,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x100b3215,
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.temp_alert_config = 0x08000a05,
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.emif_ddr_phy_ctlr_1_init = 0x0E30400d,
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.emif_ddr_phy_ctlr_1 = 0x0E30400d,
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.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x28C518A3,
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.emif_ddr_ext_phy_ctrl_3 = 0x518A3146,
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.emif_ddr_ext_phy_ctrl_4 = 0x0014628C,
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.emif_ddr_ext_phy_ctrl_5 = 0xC330CC33,
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};
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const struct emif_regs emif_regs_266_mhz_2cs = {
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.sdram_config_init = 0x80800EBA,
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.sdram_config = 0x808022BA,
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.ref_ctrl = 0x0000040D,
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.sdram_tim1 = 0x2A86B419,
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.sdram_tim2 = 0x1025094A,
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.sdram_tim3 = 0x026BA22F,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x000b3215,
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.temp_alert_config = 0x08000a05,
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.emif_ddr_phy_ctlr_1_init = 0x0E28420d,
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.emif_ddr_phy_ctlr_1 = 0x0E28420d,
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.emif_ddr_ext_phy_ctrl_1 = 0x04020080,
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.emif_ddr_ext_phy_ctrl_2 = 0x0A414829,
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.emif_ddr_ext_phy_ctrl_3 = 0x14829052,
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.emif_ddr_ext_phy_ctrl_4 = 0x000520A4,
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.emif_ddr_ext_phy_ctrl_5 = 0x04010040
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};
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const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
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.sdram_config_init = 0x61851B32,
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.sdram_config = 0x61851B32,
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.ref_ctrl = 0x00001035,
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.sdram_tim1 = 0xCCCF36B3,
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.sdram_tim2 = 0x308F7FDA,
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.sdram_tim3 = 0x027F88A8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x0007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0020420A,
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.emif_ddr_phy_ctlr_1 = 0x0024420A,
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.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_5 = 0x04010040,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x00000305
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};
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const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
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.sdram_config_init = 0x61851B32,
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.sdram_config = 0x61851B32,
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.ref_ctrl = 0x00001035,
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.sdram_tim1 = 0xCCCF36B3,
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.sdram_tim2 = 0x308F7FDA,
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.sdram_tim3 = 0x027F88A8,
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.read_idle_ctrl = 0x00050000,
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.zq_config = 0x1007190B,
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.temp_alert_config = 0x00000000,
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.emif_ddr_phy_ctlr_1_init = 0x0030400A,
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.emif_ddr_phy_ctlr_1 = 0x0034400A,
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.emif_ddr_ext_phy_ctrl_1 = 0x04040100,
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.emif_ddr_ext_phy_ctrl_2 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_3 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_4 = 0x00000000,
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.emif_ddr_ext_phy_ctrl_5 = 0x4350D435,
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.emif_rd_wr_lvl_rmp_win = 0x00000000,
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.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
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.emif_rd_wr_lvl_ctl = 0x00000000,
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.emif_rd_wr_exec_thresh = 0x40000305
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};
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const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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.dmm_lisa_map_2 = 0x80740300,
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.dmm_lisa_map_3 = 0xFF020100,
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.is_ma_present = 0x1
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};
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const struct dmm_lisa_map_regs lisa_map_512M_x_1 = {
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.dmm_lisa_map_0 = 0x0,
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.dmm_lisa_map_1 = 0x0,
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.dmm_lisa_map_2 = 0x0,
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.dmm_lisa_map_3 = 0x80500100,
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.is_ma_present = 0x1
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};
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static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
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{
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switch (omap_revision()) {
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case OMAP5430_ES1_0:
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*regs = &emif_regs_532_mhz_2cs;
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break;
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case OMAP5432_ES1_0:
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*regs = &emif_regs_ddr3_532_mhz_1cs;
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break;
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case OMAP5430_ES2_0:
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*regs = &emif_regs_532_mhz_2cs_es2;
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break;
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case OMAP5432_ES2_0:
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case DRA752_ES1_0:
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default:
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*regs = &emif_regs_ddr3_532_mhz_1cs_es2;
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}
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}
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void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
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__attribute__((weak, alias("emif_get_reg_dump_sdp")));
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static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
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**dmm_lisa_regs)
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{
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switch (omap_revision()) {
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case OMAP5430_ES1_0:
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case OMAP5430_ES2_0:
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case OMAP5432_ES1_0:
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case OMAP5432_ES2_0:
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*dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
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break;
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case DRA752_ES1_0:
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default:
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*dmm_lisa_regs = &lisa_map_512M_x_1;
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}
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}
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void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
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__attribute__((weak, alias("emif_get_dmm_regs_sdp")));
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#else
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static const struct lpddr2_device_details dev_4G_S4_details = {
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.type = LPDDR2_TYPE_S4,
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.density = LPDDR2_DENSITY_4Gb,
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.io_width = LPDDR2_IO_WIDTH_32,
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.manufacturer = LPDDR2_MANUFACTURER_SAMSUNG
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};
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static void emif_get_device_details_sdp(u32 emif_nr,
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struct lpddr2_device_details *cs0_device_details,
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struct lpddr2_device_details *cs1_device_details)
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{
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/* EMIF1 & EMIF2 have identical configuration */
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*cs0_device_details = dev_4G_S4_details;
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*cs1_device_details = dev_4G_S4_details;
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}
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void emif_get_device_details(u32 emif_nr,
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struct lpddr2_device_details *cs0_device_details,
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struct lpddr2_device_details *cs1_device_details)
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__attribute__((weak, alias("emif_get_device_details_sdp")));
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#endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
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const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
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0x01004010,
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0x00001004,
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0x04010040,
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0x01004010,
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0x00001004,
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0x00000000,
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0x00000000,
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0x00000000,
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0x80080080,
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0x00800800,
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0x08102040,
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0x00000001,
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0x540A8150,
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0xA81502a0,
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0x002A0540,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000077
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};
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const u32 ddr3_ext_phy_ctrl_const_base_es1[EMIF_EXT_PHY_CTRL_CONST_REG] = {
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0x01004010,
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0x00001004,
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0x04010040,
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0x01004010,
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0x00001004,
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0x00000000,
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0x00000000,
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0x00000000,
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0x80080080,
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0x00800800,
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0x08102040,
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0x00000002,
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0x0,
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0x0,
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0x0,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000057
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};
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const u32 ddr3_ext_phy_ctrl_const_base_es2[EMIF_EXT_PHY_CTRL_CONST_REG] = {
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0x50D4350D,
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0x00000D43,
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0x04010040,
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0x01004010,
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0x00001004,
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0x00000000,
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0x00000000,
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0x00000000,
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0x80080080,
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0x00800800,
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0x08102040,
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0x00000002,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000000,
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0x00000057
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};
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const struct lpddr2_mr_regs mr_regs = {
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.mr1 = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
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.mr2 = 0x6,
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.mr3 = 0x1,
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.mr10 = MR10_ZQ_ZQINIT,
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.mr16 = MR16_REF_FULL_ARRAY
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};
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static void emif_get_ext_phy_ctrl_const_regs(const u32 **regs)
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{
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switch (omap_revision()) {
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case OMAP5430_ES1_0:
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case OMAP5430_ES2_0:
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*regs = ext_phy_ctrl_const_base;
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break;
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case OMAP5432_ES1_0:
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*regs = ddr3_ext_phy_ctrl_const_base_es1;
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break;
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case OMAP5432_ES2_0:
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case DRA752_ES1_0:
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default:
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*regs = ddr3_ext_phy_ctrl_const_base_es2;
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}
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}
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void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
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{
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*regs = &mr_regs;
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}
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void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
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{
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u32 *ext_phy_ctrl_base = 0;
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u32 *emif_ext_phy_ctrl_base = 0;
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const u32 *ext_phy_ctrl_const_regs;
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u32 i = 0;
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struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
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ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
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emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
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/* Configure external phy control timing registers */
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for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
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writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
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/* Update shadow registers */
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writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
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}
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/*
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* external phy 6-24 registers do not change with
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* ddr frequency
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*/
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emif_get_ext_phy_ctrl_const_regs(&ext_phy_ctrl_const_regs);
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for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
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writel(ext_phy_ctrl_const_regs[i],
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emif_ext_phy_ctrl_base++);
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/* Update shadow registers */
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writel(ext_phy_ctrl_const_regs[i],
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emif_ext_phy_ctrl_base++);
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}
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}
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#ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
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static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
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.max_freq = 532000000,
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.RL = 8,
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.tRPab = 21,
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.tRCD = 18,
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.tWR = 15,
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.tRASmin = 42,
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.tRRD = 10,
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.tWTRx2 = 15,
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.tXSR = 140,
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.tXPx2 = 15,
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.tRFCab = 130,
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.tRTPx2 = 15,
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.tCKE = 3,
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.tCKESR = 15,
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.tZQCS = 90,
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.tZQCL = 360,
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.tZQINIT = 1000,
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.tDQSCKMAXx2 = 11,
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.tRASmax = 70,
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.tFAW = 50
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};
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static const struct lpddr2_min_tck min_tck = {
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.tRL = 3,
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.tRP_AB = 3,
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.tRCD = 3,
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.tWR = 3,
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.tRAS_MIN = 3,
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.tRRD = 2,
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.tWTR = 2,
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.tXP = 2,
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.tRTP = 2,
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.tCKE = 3,
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.tCKESR = 3,
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.tFAW = 8
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};
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static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
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&timings_jedec_532_mhz
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};
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static const struct lpddr2_device_timings dev_4G_S4_timings = {
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.ac_timings = ac_timings,
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.min_tck = &min_tck,
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};
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void emif_get_device_timings_sdp(u32 emif_nr,
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const struct lpddr2_device_timings **cs0_device_timings,
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const struct lpddr2_device_timings **cs1_device_timings)
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{
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/* Identical devices on EMIF1 & EMIF2 */
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*cs0_device_timings = &dev_4G_S4_timings;
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*cs1_device_timings = &dev_4G_S4_timings;
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}
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void emif_get_device_timings(u32 emif_nr,
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const struct lpddr2_device_timings **cs0_device_timings,
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const struct lpddr2_device_timings **cs1_device_timings)
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__attribute__((weak, alias("emif_get_device_timings_sdp")));
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#endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
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