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0f347a0096
The DP83867 has a muxing option for the CLK_OUT pin. It is possible
to set CLK_OUT for different channels.
Create a binding to select a specific clock for CLK_OUT pin.
Based on commit 9708fb630d19 ("net: phy: dp83867: Add binding for
the CLK_OUT pin muxing option") of mainline linux kernel.
Signed-off-by: Janine Hagemann <j.hagemann@phytec.de>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
49 lines
1.6 KiB
C
49 lines
1.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* TI DP83867 PHY drivers
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*
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*/
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#ifndef _DT_BINDINGS_TI_DP83867_H
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#define _DT_BINDINGS_TI_DP83867_H
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/* PHY CTRL bits */
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#define DP83867_PHYCR_FIFO_DEPTH_3_B_NIB 0x00
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#define DP83867_PHYCR_FIFO_DEPTH_4_B_NIB 0x01
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#define DP83867_PHYCR_FIFO_DEPTH_6_B_NIB 0x02
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#define DP83867_PHYCR_FIFO_DEPTH_8_B_NIB 0x03
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/* RGMIIDCTL internal delay for rx and tx */
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#define DP83867_RGMIIDCTL_250_PS 0x0
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#define DP83867_RGMIIDCTL_500_PS 0x1
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#define DP83867_RGMIIDCTL_750_PS 0x2
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#define DP83867_RGMIIDCTL_1_NS 0x3
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#define DP83867_RGMIIDCTL_1_25_NS 0x4
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#define DP83867_RGMIIDCTL_1_50_NS 0x5
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#define DP83867_RGMIIDCTL_1_75_NS 0x6
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#define DP83867_RGMIIDCTL_2_00_NS 0x7
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#define DP83867_RGMIIDCTL_2_25_NS 0x8
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#define DP83867_RGMIIDCTL_2_50_NS 0x9
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#define DP83867_RGMIIDCTL_2_75_NS 0xa
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#define DP83867_RGMIIDCTL_3_00_NS 0xb
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#define DP83867_RGMIIDCTL_3_25_NS 0xc
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#define DP83867_RGMIIDCTL_3_50_NS 0xd
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#define DP83867_RGMIIDCTL_3_75_NS 0xe
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#define DP83867_RGMIIDCTL_4_00_NS 0xf
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/* IO_MUX_CFG - Clock output selection */
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#define DP83867_CLK_O_SEL_CHN_A_RCLK 0x0
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#define DP83867_CLK_O_SEL_CHN_B_RCLK 0x1
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#define DP83867_CLK_O_SEL_CHN_C_RCLK 0x2
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#define DP83867_CLK_O_SEL_CHN_D_RCLK 0x3
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#define DP83867_CLK_O_SEL_CHN_A_RCLK_DIV5 0x4
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#define DP83867_CLK_O_SEL_CHN_B_RCLK_DIV5 0x5
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#define DP83867_CLK_O_SEL_CHN_C_RCLK_DIV5 0x6
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#define DP83867_CLK_O_SEL_CHN_D_RCLK_DIV5 0x7
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#define DP83867_CLK_O_SEL_CHN_A_TCLK 0x8
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#define DP83867_CLK_O_SEL_CHN_B_TCLK 0x9
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#define DP83867_CLK_O_SEL_CHN_C_TCLK 0xA
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#define DP83867_CLK_O_SEL_CHN_D_TCLK 0xB
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#define DP83867_CLK_O_SEL_REF_CLK 0xC
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#endif
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