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845102cbe9
The kmtegr1 board is out of maintenance and can be removed. As it is the only board in the tree using MPC8309 the support for this CPU is dropped completely. Signed-off-by: Holger Brunck <holger.brunck@hitachienergy.com>
559 lines
12 KiB
C
559 lines
12 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2000-2002
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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*/
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#ifndef CONFIG_CLK_MPC83XX
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#include <common.h>
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#include <clock_legacy.h>
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#include <mpc83xx.h>
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#include <command.h>
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#include <vsprintf.h>
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#include <asm/global_data.h>
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#include <asm/processor.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* ----------------------------------------------------------------- */
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typedef enum {
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_unk,
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_off,
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_byp,
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_x8,
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_x4,
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_x2,
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_x1,
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_1x,
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_1_5x,
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_2x,
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_2_5x,
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_3x
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} mult_t;
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typedef struct {
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mult_t core_csb_ratio;
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mult_t vco_divider;
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} corecnf_t;
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static corecnf_t corecnf_tab[] = {
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{_byp, _byp}, /* 0x00 */
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{_byp, _byp}, /* 0x01 */
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{_byp, _byp}, /* 0x02 */
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{_byp, _byp}, /* 0x03 */
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{_byp, _byp}, /* 0x04 */
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{_byp, _byp}, /* 0x05 */
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{_byp, _byp}, /* 0x06 */
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{_byp, _byp}, /* 0x07 */
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{_1x, _x2}, /* 0x08 */
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{_1x, _x4}, /* 0x09 */
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{_1x, _x8}, /* 0x0A */
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{_1x, _x8}, /* 0x0B */
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{_1_5x, _x2}, /* 0x0C */
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{_1_5x, _x4}, /* 0x0D */
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{_1_5x, _x8}, /* 0x0E */
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{_1_5x, _x8}, /* 0x0F */
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{_2x, _x2}, /* 0x10 */
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{_2x, _x4}, /* 0x11 */
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{_2x, _x8}, /* 0x12 */
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{_2x, _x8}, /* 0x13 */
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{_2_5x, _x2}, /* 0x14 */
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{_2_5x, _x4}, /* 0x15 */
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{_2_5x, _x8}, /* 0x16 */
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{_2_5x, _x8}, /* 0x17 */
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{_3x, _x2}, /* 0x18 */
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{_3x, _x4}, /* 0x19 */
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{_3x, _x8}, /* 0x1A */
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{_3x, _x8}, /* 0x1B */
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};
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/* ----------------------------------------------------------------- */
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/*
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*
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*/
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int get_clocks(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 pci_sync_in;
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u8 spmf;
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u8 clkin_div;
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u32 sccr;
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u32 corecnf_tab_index;
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u8 corepll;
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u32 lcrr;
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u32 csb_clk;
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
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u32 tsec1_clk;
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u32 tsec2_clk;
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u32 usbdr_clk;
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#endif
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#ifdef CONFIG_ARCH_MPC834X
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u32 usbmph_clk;
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#endif
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u32 core_clk;
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u32 i2c1_clk;
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#if !defined(CONFIG_ARCH_MPC832X)
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u32 i2c2_clk;
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#endif
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#if defined(CONFIG_FSL_ESDHC)
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u32 sdhc_clk;
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#endif
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u32 enc_clk;
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u32 lbiu_clk;
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u32 lclk_clk;
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u32 mem_clk;
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#if defined(CONFIG_ARCH_MPC8360)
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u32 mem_sec_clk;
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#endif
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#if defined(CONFIG_QE)
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u32 qepmf;
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u32 qepdf;
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u32 qe_clk;
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u32 brg_clk;
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#endif
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC837X)
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u32 pciexp1_clk;
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u32 pciexp2_clk;
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#endif
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#if defined(CONFIG_ARCH_MPC837X)
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u32 sata_clk;
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#endif
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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clkin_div = ((im->clk.spmr & SPMR_CKID) >> SPMR_CKID_SHIFT);
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if (im->reset.rcwh & HRCWH_PCI_HOST) {
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#if CONFIG_SYS_CLK_FREQ != 0
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pci_sync_in = get_board_sys_clk() / (1 + clkin_div);
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#else
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pci_sync_in = 0xDEADBEEF;
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#endif
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} else {
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#if defined(CONFIG_83XX_PCICLK)
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pci_sync_in = CONFIG_83XX_PCICLK;
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#else
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pci_sync_in = 0xDEADBEEF;
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#endif
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}
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spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
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csb_clk = pci_sync_in * (1 + clkin_div) * spmf;
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sccr = im->clk.sccr;
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
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switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
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case 0:
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tsec1_clk = 0;
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break;
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case 1:
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tsec1_clk = csb_clk;
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break;
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case 2:
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tsec1_clk = csb_clk / 2;
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break;
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case 3:
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tsec1_clk = csb_clk / 3;
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break;
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default:
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/* unknown SCCR_TSEC1CM value */
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return -2;
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}
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#endif
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#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
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switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
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case 0:
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usbdr_clk = 0;
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break;
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case 1:
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usbdr_clk = csb_clk;
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break;
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case 2:
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usbdr_clk = csb_clk / 2;
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break;
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case 3:
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usbdr_clk = csb_clk / 3;
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break;
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default:
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/* unknown SCCR_USBDRCM value */
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return -3;
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}
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#endif
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC834X) || \
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defined(CONFIG_ARCH_MPC837X)
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switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
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case 0:
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tsec2_clk = 0;
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break;
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case 1:
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tsec2_clk = csb_clk;
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break;
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case 2:
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tsec2_clk = csb_clk / 2;
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break;
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case 3:
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tsec2_clk = csb_clk / 3;
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break;
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default:
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/* unknown SCCR_TSEC2CM value */
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return -4;
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}
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#elif defined(CONFIG_ARCH_MPC8313)
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tsec2_clk = tsec1_clk;
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if (!(sccr & SCCR_TSEC1ON))
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tsec1_clk = 0;
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if (!(sccr & SCCR_TSEC2ON))
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tsec2_clk = 0;
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#endif
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#if defined(CONFIG_ARCH_MPC834X)
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switch ((sccr & SCCR_USBMPHCM) >> SCCR_USBMPHCM_SHIFT) {
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case 0:
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usbmph_clk = 0;
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break;
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case 1:
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usbmph_clk = csb_clk;
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break;
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case 2:
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usbmph_clk = csb_clk / 2;
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break;
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case 3:
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usbmph_clk = csb_clk / 3;
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break;
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default:
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/* unknown SCCR_USBMPHCM value */
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return -5;
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}
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if (usbmph_clk != 0 && usbdr_clk != 0 && usbmph_clk != usbdr_clk) {
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/* if USB MPH clock is not disabled and
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* USB DR clock is not disabled then
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* USB MPH & USB DR must have the same rate
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*/
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return -6;
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}
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#endif
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switch ((sccr & SCCR_ENCCM) >> SCCR_ENCCM_SHIFT) {
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case 0:
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enc_clk = 0;
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break;
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case 1:
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enc_clk = csb_clk;
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break;
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case 2:
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enc_clk = csb_clk / 2;
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break;
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case 3:
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enc_clk = csb_clk / 3;
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break;
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default:
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/* unknown SCCR_ENCCM value */
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return -7;
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}
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#if defined(CONFIG_FSL_ESDHC)
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switch ((sccr & SCCR_SDHCCM) >> SCCR_SDHCCM_SHIFT) {
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case 0:
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sdhc_clk = 0;
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break;
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case 1:
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sdhc_clk = csb_clk;
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break;
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case 2:
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sdhc_clk = csb_clk / 2;
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break;
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case 3:
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sdhc_clk = csb_clk / 3;
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break;
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default:
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/* unknown SCCR_SDHCCM value */
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return -8;
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}
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#endif
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#if defined(CONFIG_ARCH_MPC834X)
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i2c1_clk = tsec2_clk;
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#elif defined(CONFIG_ARCH_MPC8360)
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i2c1_clk = csb_clk;
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#elif defined(CONFIG_ARCH_MPC832X)
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i2c1_clk = enc_clk;
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#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
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i2c1_clk = enc_clk;
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#elif defined(CONFIG_FSL_ESDHC)
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i2c1_clk = sdhc_clk;
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#elif defined(CONFIG_ARCH_MPC837X)
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i2c1_clk = enc_clk;
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#endif
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#if !defined(CONFIG_ARCH_MPC832X)
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i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
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#endif
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC837X)
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switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
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case 0:
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pciexp1_clk = 0;
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break;
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case 1:
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pciexp1_clk = csb_clk;
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break;
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case 2:
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pciexp1_clk = csb_clk / 2;
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break;
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case 3:
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pciexp1_clk = csb_clk / 3;
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break;
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default:
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/* unknown SCCR_PCIEXP1CM value */
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return -9;
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}
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switch ((sccr & SCCR_PCIEXP2CM) >> SCCR_PCIEXP2CM_SHIFT) {
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case 0:
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pciexp2_clk = 0;
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break;
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case 1:
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pciexp2_clk = csb_clk;
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break;
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case 2:
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pciexp2_clk = csb_clk / 2;
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break;
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case 3:
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pciexp2_clk = csb_clk / 3;
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break;
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default:
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/* unknown SCCR_PCIEXP2CM value */
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return -10;
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}
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#endif
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#if defined(CONFIG_ARCH_MPC837X)
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switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
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case 0:
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sata_clk = 0;
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break;
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case 1:
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sata_clk = csb_clk;
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break;
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case 2:
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sata_clk = csb_clk / 2;
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break;
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case 3:
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sata_clk = csb_clk / 3;
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break;
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default:
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/* unknown SCCR_SATA1CM value */
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return -11;
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}
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#endif
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lbiu_clk = csb_clk *
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(1 + ((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
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lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
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switch (lcrr) {
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case 2:
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case 4:
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case 8:
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lclk_clk = lbiu_clk / lcrr;
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break;
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default:
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/* unknown lcrr */
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return -12;
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}
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mem_clk = csb_clk *
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(1 + ((im->clk.spmr & SPMR_DDRCM) >> SPMR_DDRCM_SHIFT));
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corepll = (im->clk.spmr & SPMR_COREPLL) >> SPMR_COREPLL_SHIFT;
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#if defined(CONFIG_ARCH_MPC8360)
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mem_sec_clk = csb_clk * (1 +
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((im->clk.spmr & SPMR_LBIUCM) >> SPMR_LBIUCM_SHIFT));
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#endif
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corecnf_tab_index = ((corepll & 0x1F) << 2) | ((corepll & 0x60) >> 5);
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if (corecnf_tab_index > (ARRAY_SIZE(corecnf_tab))) {
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/* corecnf_tab_index is too high, possibly wrong value */
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return -11;
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}
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switch (corecnf_tab[corecnf_tab_index].core_csb_ratio) {
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case _byp:
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case _x1:
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case _1x:
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core_clk = csb_clk;
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break;
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case _1_5x:
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core_clk = (3 * csb_clk) / 2;
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break;
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case _2x:
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core_clk = 2 * csb_clk;
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break;
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case _2_5x:
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core_clk = (5 * csb_clk) / 2;
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break;
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case _3x:
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core_clk = 3 * csb_clk;
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break;
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default:
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/* unknown core to csb ratio */
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return -13;
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}
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#if defined(CONFIG_QE)
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qepmf = (im->clk.spmr & SPMR_CEPMF) >> SPMR_CEPMF_SHIFT;
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qepdf = (im->clk.spmr & SPMR_CEPDF) >> SPMR_CEPDF_SHIFT;
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qe_clk = (pci_sync_in * qepmf) / (1 + qepdf);
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brg_clk = qe_clk / 2;
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#endif
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gd->arch.csb_clk = csb_clk;
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
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gd->arch.tsec1_clk = tsec1_clk;
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gd->arch.tsec2_clk = tsec2_clk;
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gd->arch.usbdr_clk = usbdr_clk;
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#endif
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#if defined(CONFIG_ARCH_MPC834X)
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gd->arch.usbmph_clk = usbmph_clk;
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#endif
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#if defined(CONFIG_FSL_ESDHC)
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gd->arch.sdhc_clk = sdhc_clk;
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#endif
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gd->arch.core_clk = core_clk;
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gd->arch.i2c1_clk = i2c1_clk;
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#if !defined(CONFIG_ARCH_MPC832X)
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gd->arch.i2c2_clk = i2c2_clk;
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#endif
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gd->arch.enc_clk = enc_clk;
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gd->arch.lbiu_clk = lbiu_clk;
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gd->arch.lclk_clk = lclk_clk;
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gd->mem_clk = mem_clk;
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#if defined(CONFIG_ARCH_MPC8360)
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gd->arch.mem_sec_clk = mem_sec_clk;
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#endif
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#if defined(CONFIG_QE)
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gd->arch.qe_clk = qe_clk;
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gd->arch.brg_clk = brg_clk;
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#endif
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#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
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defined(CONFIG_ARCH_MPC837X)
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gd->arch.pciexp1_clk = pciexp1_clk;
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gd->arch.pciexp2_clk = pciexp2_clk;
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#endif
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#if defined(CONFIG_ARCH_MPC837X)
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gd->arch.sata_clk = sata_clk;
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#endif
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gd->pci_clk = pci_sync_in;
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gd->cpu_clk = gd->arch.core_clk;
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gd->bus_clk = gd->arch.csb_clk;
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return 0;
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}
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/********************************************
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* get_bus_freq
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* return system bus freq in Hz
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*********************************************/
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ulong get_bus_freq(ulong dummy)
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{
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return gd->arch.csb_clk;
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}
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/********************************************
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* get_ddr_freq
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* return ddr bus freq in Hz
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*********************************************/
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ulong get_ddr_freq(ulong dummy)
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{
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return gd->mem_clk;
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}
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int get_serial_clock(void)
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{
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return get_bus_freq(0);
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}
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static int do_clocks(struct cmd_tbl *cmdtp, int flag, int argc,
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char *const argv[])
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{
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char buf[32];
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printf("Clock configuration:\n");
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printf(" Core: %-4s MHz\n",
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strmhz(buf, gd->arch.core_clk));
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printf(" Coherent System Bus: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.csb_clk));
|
|
#if defined(CONFIG_QE)
|
|
printf(" QE: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.qe_clk));
|
|
printf(" BRG: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.brg_clk));
|
|
#endif
|
|
printf(" Local Bus Controller:%-4s MHz\n",
|
|
strmhz(buf, gd->arch.lbiu_clk));
|
|
printf(" Local Bus: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.lclk_clk));
|
|
printf(" DDR: %-4s MHz\n", strmhz(buf, gd->mem_clk));
|
|
#if defined(CONFIG_ARCH_MPC8360)
|
|
printf(" DDR Secondary: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.mem_sec_clk));
|
|
#endif
|
|
printf(" SEC: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.enc_clk));
|
|
printf(" I2C1: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.i2c1_clk));
|
|
#if !defined(CONFIG_ARCH_MPC832X)
|
|
printf(" I2C2: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.i2c2_clk));
|
|
#endif
|
|
#if defined(CONFIG_FSL_ESDHC)
|
|
printf(" SDHC: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.sdhc_clk));
|
|
#endif
|
|
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
|
|
defined(CONFIG_ARCH_MPC834X) || defined(CONFIG_ARCH_MPC837X)
|
|
printf(" TSEC1: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.tsec1_clk));
|
|
printf(" TSEC2: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.tsec2_clk));
|
|
printf(" USB DR: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.usbdr_clk));
|
|
#endif
|
|
#if defined(CONFIG_ARCH_MPC834X)
|
|
printf(" USB MPH: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.usbmph_clk));
|
|
#endif
|
|
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
|
|
defined(CONFIG_ARCH_MPC837X)
|
|
printf(" PCIEXP1: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.pciexp1_clk));
|
|
printf(" PCIEXP2: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.pciexp2_clk));
|
|
#endif
|
|
#if defined(CONFIG_ARCH_MPC837X)
|
|
printf(" SATA: %-4s MHz\n",
|
|
strmhz(buf, gd->arch.sata_clk));
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
U_BOOT_CMD(clocks, 1, 0, do_clocks,
|
|
"print clock configuration",
|
|
" clocks"
|
|
);
|
|
|
|
#endif
|