mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-27 18:02:23 +00:00
a8d9758d01
C29XPCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. It includes C293PCIE board, C293PCIE board and C291PCIE board. - 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Singed-off-by: Po Liu <Po.Liu@freescale.com> [yorksun: Fixup include/configs/C29XPCIE.h] Signed-off-by: York Sun <yorksun@freescale.com>
79 lines
2.5 KiB
C
79 lines
2.5 KiB
C
/*
|
|
* Copyright 2013 Freescale Semiconductor, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the Free
|
|
* Software Foundation; either version 2 of the License, or (at your option)
|
|
* any later version.
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/mmu.h>
|
|
|
|
struct fsl_e_tlb_entry tlb_table[] = {
|
|
/* TLB 0 - for temp stack in cache */
|
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
|
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
|
|
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
|
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
|
|
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
|
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
|
|
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
|
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
|
|
/* TLB 1 */
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 0, BOOKE_PAGESZ_1M, 1),
|
|
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
|
|
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
|
0, 1, BOOKE_PAGESZ_64M, 1),
|
|
|
|
#ifdef CONFIG_PCI
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 2, BOOKE_PAGESZ_256M, 1),
|
|
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 3, BOOKE_PAGESZ_256K, 1),
|
|
#endif
|
|
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 4, BOOKE_PAGESZ_4K, 1),
|
|
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
|
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
0, 5, BOOKE_PAGESZ_16K, 1),
|
|
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
|
|
CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,
|
|
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
0, 6, BOOKE_PAGESZ_256K, 1),
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
|
|
CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,
|
|
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
0, 7, BOOKE_PAGESZ_256K, 1),
|
|
|
|
#ifdef CONFIG_SYS_RAMBOOT
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
|
|
CONFIG_SYS_DDR_SDRAM_BASE,
|
|
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
0, 8, BOOKE_PAGESZ_256M, 1),
|
|
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
|
|
CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
|
|
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
0, 9, BOOKE_PAGESZ_256M, 1),
|
|
#endif
|
|
};
|
|
|
|
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|