mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-20 11:43:22 +00:00
a8d9758d01
C29XPCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. It includes C293PCIE board, C293PCIE board and C291PCIE board. - 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Singed-off-by: Po Liu <Po.Liu@freescale.com> [yorksun: Fixup include/configs/C29XPCIE.h] Signed-off-by: York Sun <yorksun@freescale.com>
43 lines
1.6 KiB
C
43 lines
1.6 KiB
C
/**
|
|
* Copyright 2013 Freescale Semiconductor
|
|
* Author: Mingkai Hu <Mingkai.Hu@freescale.com>
|
|
* Po Liu <Po.Liu@freescale.com>
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
* under the terms of the GNU General Public License as published by the Free
|
|
* Software Foundation; either version 2 of the License, or (at your option)
|
|
* any later version.
|
|
*
|
|
* This file provides support for the ngPIXIS, a board-specific FPGA used on
|
|
* some Freescale reference boards.
|
|
*/
|
|
|
|
/*
|
|
* CPLD register set. Feel free to add board-specific #ifdefs where necessary.
|
|
*/
|
|
struct cpld_data {
|
|
u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */
|
|
u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */
|
|
u8 hwver; /* 0x2 - Hardware Version Register */
|
|
u8 cpldver; /* 0x3 - Software Version Register */
|
|
u8 res[12];
|
|
u8 rstcon; /* 0x10 - Reset control register */
|
|
u8 flhcsr; /* 0x11 - Flash control and status Register */
|
|
u8 wdcsr; /* 0x12 - Watchdog control and status Register */
|
|
u8 wdkick; /* 0x13 - Watchdog kick Register */
|
|
u8 fancsr; /* 0x14 - Fan control and status Register */
|
|
u8 ledcsr; /* 0x15 - LED control and status Register */
|
|
u8 misccsr; /* 0x16 - Misc control and status Register */
|
|
u8 bootor; /* 0x17 - Boot configure override Register */
|
|
u8 bootcfg1; /* 0x18 - Boot configure 1 Register */
|
|
u8 bootcfg2; /* 0x19 - Boot configure 2 Register */
|
|
u8 bootcfg3; /* 0x1a - Boot configure 3 Register */
|
|
u8 bootcfg4; /* 0x1b - Boot configure 4 Register */
|
|
};
|
|
|
|
#define CPLD_BANKSEL_EN 0x02
|
|
#define CPLD_BANKSEL_MASK 0x3f
|
|
#define CPLD_SELECT_BANK1 0xc0
|
|
#define CPLD_SELECT_BANK2 0x80
|
|
#define CPLD_SELECT_BANK3 0x40
|
|
#define CPLD_SELECT_BANK4 0x00
|