mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-29 14:33:08 +00:00
a9221f3ebd
Enable the extended ENV options for AT91 and OMAP2PLUS in order to be
able to use CONFIG_ENV_UBI_* on these architectures.
As this change also makes the configs ENV_SIZE, ENV_SECT_SIZE,
ENV_OFFSET visible to AT91 and OMAP2PLUS, migrate users of these to
KConfig.
This migration was run using an extended moveconfig.py which evaluates
expressions such as "(512 << 10)". See patch ("moveconfig: expand
simple expressions").
All modified boards were built with SOURCE_DATE_EPOCH=0 before and
after the change and successfully confirmed that the identical binary
is generated (the only exception was igep00x0, which does not define
CONFIG_ENV_IS_IN_UBI in the original board header. Once that is
defined, the test passes too).
hs: rebased patch to:
68b90e57bc: "configs: tinker-rk3288 disable CONFIG_SPL_I2C_SUPPORT"
Signed-off-by: Markus Klotzbuecher <markus.klotzbuecher@kistler.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Eugen Hristev <eugen.hristev@microchip.com>
Cc: Tom Rini <trini@konsulko.com>
150 lines
4.1 KiB
C
150 lines
4.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2011
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* egnite GmbH <info@egnite.de>
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*
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* Configuation settings for Ethernut 5 with AT91SAM9XE.
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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#include <asm/hardware.h>
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/* The first stage boot loader expects u-boot running at this address. */
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/* The first stage boot loader takes care of low level initialization. */
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#define CONFIG_SKIP_LOWLEVEL_INIT
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/* Set our official architecture number. */
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#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
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/* CPU information */
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#define CONFIG_ARCH_CPU_INIT
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/* ARM asynchronous clock */
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#define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */
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#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432 MHz crystal */
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/* 32kB internal SRAM */
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#define CONFIG_SRAM_BASE 0x00300000 /*AT91SAM9XE_SRAM_BASE */
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#define CONFIG_SRAM_SIZE (32 << 10)
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
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GENERATED_GBL_DATA_SIZE)
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/* 128MB SDRAM in 1 bank */
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#define CONFIG_SYS_SDRAM_BASE 0x20000000
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#define CONFIG_SYS_SDRAM_SIZE (128 << 20)
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#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE
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#define CONFIG_LOADADDR CONFIG_SYS_LOAD_ADDR
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
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#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE \
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- CONFIG_SYS_MALLOC_LEN)
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/* 512kB on-chip NOR flash */
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# define CONFIG_SYS_MAX_FLASH_BANKS 1
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# define CONFIG_SYS_FLASH_BASE 0x00200000 /* AT91SAM9XE_FLASH_BASE */
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# define CONFIG_AT91_EFLASH
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# define CONFIG_SYS_MAX_FLASH_SECT 32
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# define CONFIG_EFLASH_PROTSECTORS 1
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/* bootstrap + u-boot + env + linux in dataflash on CS0 */
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#define CONFIG_ENV_OFFSET 0x3DE000
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/* NAND flash */
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#ifdef CONFIG_CMD_NAND
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_DBW_8
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/* our ALE is AD21 */
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#define CONFIG_SYS_NAND_MASK_ALE (1 << 21)
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/* our CLE is AD22 */
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#define CONFIG_SYS_NAND_MASK_CLE (1 << 22)
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#define CONFIG_SYS_NAND_ENABLE_PIN GPIO_PIN_PC(14)
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#endif
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/* JFFS2 */
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#ifdef CONFIG_CMD_JFFS2
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#define CONFIG_JFFS2_CMDLINE
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#define CONFIG_JFFS2_NAND
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#endif
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/* Ethernet */
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#define CONFIG_NET_RETRY_COUNT 20
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#define CONFIG_MACB
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#define CONFIG_RMII
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#define CONFIG_PHY_ID 0
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#define CONFIG_MACB_SEARCH_PHY
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/* MMC */
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#ifdef CONFIG_CMD_MMC
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#define CONFIG_GENERIC_ATMEL_MCI
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#define CONFIG_SYS_MMC_CD_PIN AT91_PIO_PORTC, 8
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#endif
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/* USB */
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#ifdef CONFIG_CMD_USB
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#define CONFIG_USB_ATMEL
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#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
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#define CONFIG_USB_OHCI_NEW
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#define CONFIG_SYS_USB_OHCI_CPU_INIT
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#define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000
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#define CONFIG_SYS_USB_OHCI_SLOT_NAME "host"
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#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
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#endif
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/* RTC */
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#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
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#define CONFIG_RTC_PCF8563
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51
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#endif
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/* I2C */
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#define CONFIG_SYS_MAX_I2C_BUS 1
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
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#define CONFIG_SYS_I2C_SOFT_SPEED 100000
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#define CONFIG_SYS_I2C_SOFT_SLAVE 0
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#define I2C_SOFT_DECLARATIONS
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#define GPIO_I2C_SCL AT91_PIO_PORTA, 24
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#define GPIO_I2C_SDA AT91_PIO_PORTA, 23
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#define I2C_INIT { \
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at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
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at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
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at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
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at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
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at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
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}
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#define I2C_ACTIVE at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
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#define I2C_TRISTATE at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
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#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
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#define I2C_SDA(bit) at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
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#define I2C_DELAY udelay(100)
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#define I2C_READ at91_get_pio_value(AT91_PIO_PORTA, 23)
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/* DHCP/BOOTP options */
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#ifdef CONFIG_CMD_DHCP
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#define CONFIG_BOOTP_BOOTFILESIZE
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#define CONFIG_SYS_AUTOLOAD "n"
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#endif
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/* File systems */
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/* Boot command */
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#define CONFIG_CMDLINE_TAG
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#define CONFIG_SETUP_MEMORY_TAGS
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#define CONFIG_INITRD_TAG
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#define CONFIG_BOOTCOMMAND "sf probe 0:0; " \
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"sf read 0x22000000 0xc6000 0x294000; " \
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"bootm 0x22000000"
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/* Misc. u-boot settings */
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#endif
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