mirror of
https://github.com/AsahiLinux/u-boot
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fe7d654d04
Migrate the BR/OR settings to Kconfig. These must be known at compile time, so cannot be configured via DT. Configuration of this crucial variable should still be somewhat comfortable. Hence, make its fields configurable in Kconfig, and assemble the final value from these. Signed-off-by: Mario Six <mario.six@gdsys.cc>
418 lines
12 KiB
C
418 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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* Dave Liu <daveliu@freescale.com>
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*/
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#ifndef __CONFIG_H
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#define __CONFIG_H
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/*
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* High Level Configuration Options
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*/
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#define CONFIG_E300 1 /* E300 family */
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/* Arbiter Configuration Register */
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#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
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#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
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/* System Priority Control Register */
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#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
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/*
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* IP blocks clock configuration
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*/
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#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
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#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
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#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
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/*
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* System IO Config
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*/
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#define CONFIG_SYS_SICRH 0x00000000
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#define CONFIG_SYS_SICRL 0x00000000
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/*
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* Output Buffer Impedance
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*/
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#define CONFIG_SYS_OBIR 0x31100000
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#define CONFIG_HWCONFIG
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/*
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* IMMR new address
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*/
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#define CONFIG_SYS_IMMR 0xE0000000
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/*
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* DDR Setup
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*/
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#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
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#define CONFIG_SYS_83XX_DDR_USES_CS0
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#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
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| DDRCDR_ODT \
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| DDRCDR_Q_DRN)
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/* 0x80080001 */ /* ODT 150ohm on SoC */
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#undef CONFIG_DDR_ECC /* support DDR ECC function */
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#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
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#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
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#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
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#if defined(CONFIG_SPD_EEPROM)
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#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
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#else
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/*
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* Manually set up DDR parameters
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* WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
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* consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
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*/
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#define CONFIG_SYS_DDR_SIZE 512 /* MB */
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#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
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#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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| CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
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| CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
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| CSCONFIG_ROW_BIT_14 \
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| CSCONFIG_COL_BIT_10)
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/* 0x80010202 */
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#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
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| (0 << TIMING_CFG0_WRT_SHIFT) \
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| (0 << TIMING_CFG0_RRT_SHIFT) \
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| (0 << TIMING_CFG0_WWT_SHIFT) \
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| (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
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| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
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| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
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/* 0x00620802 */
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#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
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| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
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| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
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| (5 << TIMING_CFG1_CASLAT_SHIFT) \
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| (13 << TIMING_CFG1_REFREC_SHIFT) \
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| (3 << TIMING_CFG1_WRREC_SHIFT) \
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| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
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| (2 << TIMING_CFG1_WRTORD_SHIFT))
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/* 0x3935d322 */
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#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
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| (6 << TIMING_CFG2_CPO_SHIFT) \
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| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
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| (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
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| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
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| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
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| (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
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/* 0x131088c8 */
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#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
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| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
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/* 0x03E00100 */
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#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
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#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
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#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
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| (0x1432 << SDRAM_MODE_SD_SHIFT))
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/* ODT 150ohm CL=3, AL=1 on SDRAM */
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#define CONFIG_SYS_DDR_MODE2 0x00000000
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#endif
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/*
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* Memory test
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*/
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#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
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#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
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#define CONFIG_SYS_MEMTEST_END 0x00140000
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/*
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* The reserved memory
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*/
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
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#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
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#define CONFIG_SYS_RAMBOOT
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#else
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#undef CONFIG_SYS_RAMBOOT
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#endif
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/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
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#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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/*
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* Initial RAM Base Address Setup
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*/
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#define CONFIG_SYS_INIT_RAM_LOCK 1
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#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
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#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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#define CONFIG_SYS_GBL_DATA_OFFSET \
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(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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/*
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* Local Bus Configuration & Clock Setup
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*/
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#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
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#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
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#define CONFIG_SYS_LBC_LBCR 0x00000000
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#define CONFIG_FSL_ELBC 1
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/*
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* FLASH on the Local Bus
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*/
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#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
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#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
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#undef CONFIG_SYS_FLASH_CHECKSUM
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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/*
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* BCSR on the Local Bus
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*/
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#define CONFIG_SYS_BCSR 0xF8000000
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/* Access window base at BCSR base */
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/*
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* NAND Flash on the Local Bus
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*/
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_NAND_FSL_ELBC 1
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#define CONFIG_SYS_NAND_BASE 0xE0600000
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/*
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* Serial Port
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*/
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
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#define CONFIG_SYS_BAUDRATE_TABLE \
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{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
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#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
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#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_FSL
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#define CONFIG_SYS_FSL_I2C_SPEED 400000
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#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
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#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
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#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
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/*
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* Config on-board RTC
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*/
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#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
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#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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/*
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* General PCI
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* Addresses are mapped 1-1.
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*/
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#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
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#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
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#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
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#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
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#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
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#define CONFIG_SYS_PCI_IO_BASE 0x00000000
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#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
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#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
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#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
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#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
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#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
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#define CONFIG_SYS_PCIE1_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
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#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
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#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
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#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
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#define CONFIG_SYS_PCIE2_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
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#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
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#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
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#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
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#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
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#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
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#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
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#ifdef CONFIG_PCI
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#define CONFIG_PCI_INDIRECT_BRIDGE
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#ifndef __ASSEMBLY__
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extern int board_pci_host_broken(void);
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#endif
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#define CONFIG_PCIE
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#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
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#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
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#define CONFIG_USB_EHCI_FSL
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
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#undef CONFIG_EEPRO100
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#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
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#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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#endif /* CONFIG_PCI */
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/*
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* TSEC
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*/
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#define CONFIG_SYS_TSEC1_OFFSET 0x24000
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#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
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#define CONFIG_SYS_TSEC2_OFFSET 0x25000
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#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
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/*
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* TSEC ethernet configuration
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*/
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#define CONFIG_TSEC1 1
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#define CONFIG_TSEC1_NAME "eTSEC0"
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#define CONFIG_TSEC2 1
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#define CONFIG_TSEC2_NAME "eTSEC1"
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#define TSEC1_PHY_ADDR 2
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#define TSEC2_PHY_ADDR 3
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#define TSEC1_PHY_ADDR_SGMII 8
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#define TSEC2_PHY_ADDR_SGMII 4
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#define TSEC1_PHYIDX 0
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#define TSEC2_PHYIDX 0
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#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
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/* Options are: TSEC[0-1] */
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#define CONFIG_ETHPRIME "eTSEC1"
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/* SERDES */
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#define CONFIG_FSL_SERDES
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#define CONFIG_FSL_SERDES1 0xe3000
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#define CONFIG_FSL_SERDES2 0xe3100
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/*
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* SATA
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*/
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#define CONFIG_SYS_SATA_MAX_DEVICE 2
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#define CONFIG_SATA1
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#define CONFIG_SYS_SATA1_OFFSET 0x18000
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#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
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#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
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#define CONFIG_SATA2
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#define CONFIG_SYS_SATA2_OFFSET 0x19000
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#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
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#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
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#ifdef CONFIG_FSL_SATA
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#define CONFIG_LBA48
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#endif
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/*
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* Environment
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*/
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#ifndef CONFIG_SYS_RAMBOOT
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#define CONFIG_ENV_ADDR \
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(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
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#define CONFIG_ENV_SIZE 0x2000
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#endif
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#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
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#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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/*
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* BOOTP options
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*/
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#define CONFIG_BOOTP_BOOTFILESIZE
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/*
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* Command line configuration.
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*/
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#undef CONFIG_WATCHDOG /* watchdog disabled */
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#ifdef CONFIG_MMC
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#define CONFIG_FSL_ESDHC_PIN_MUX
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#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
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#endif
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/*
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* Miscellaneous configurable options
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*/
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#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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/*
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* For booting Linux, the board info and command line data
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* have to be in the first 256 MB of memory, since this is
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* the maximum mapped by the Linux kernel during initialization.
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*/
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#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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/*
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* Core HID Setup
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*/
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#define CONFIG_SYS_HID0_INIT 0x000000000
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#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
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HID0_ENABLE_INSTRUCTION_CACHE)
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#define CONFIG_SYS_HID2 HID2_HBE
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#if defined(CONFIG_CMD_KGDB)
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#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
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#endif
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/*
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* Environment Configuration
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*/
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#define CONFIG_ENV_OVERWRITE
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#if defined(CONFIG_TSEC_ENET)
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#define CONFIG_HAS_ETH0
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#define CONFIG_HAS_ETH1
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#endif
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#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"netdev=eth0\0" \
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"consoledev=ttyS0\0" \
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"ramdiskaddr=1000000\0" \
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"ramdiskfile=ramfs.83xx\0" \
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"fdtaddr=780000\0" \
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"fdtfile=mpc8379_mds.dtb\0" \
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""
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#define CONFIG_NFSBOOTCOMMAND \
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"setenv bootargs root=/dev/nfs rw " \
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"nfsroot=$serverip:$rootpath " \
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"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
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"$netdev:off " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr - $fdtaddr"
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#define CONFIG_RAMBOOTCOMMAND \
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"setenv bootargs root=/dev/ram rw " \
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"console=$consoledev,$baudrate $othbootargs;" \
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"tftp $ramdiskaddr $ramdiskfile;" \
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"tftp $loadaddr $bootfile;" \
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"tftp $fdtaddr $fdtfile;" \
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"bootm $loadaddr $ramdiskaddr $fdtaddr"
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#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
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#endif /* __CONFIG_H */
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