mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-02 17:41:08 +00:00
8f1a80e99e
Migrate all remaining instances of CMD_NAND, CMD_NAND_TRIMFFS CMD_NAND_LOCK_UNLOCK and CMD_NAND_TORTURE from the headers into the defconfig files. Tested-by: Adam Ford <aford173@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
90 lines
2.8 KiB
C
90 lines
2.8 KiB
C
/*
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* Copyright (C) 2012 Freescale Semiconductor, Inc.
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*
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* Configuration settings for the Freescale i.MX6Q SabreAuto board.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __MX6SABREAUTO_CONFIG_H
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#define __MX6SABREAUTO_CONFIG_H
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#ifdef CONFIG_SPL
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#include "imx6_spl.h"
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#endif
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#define CONFIG_MACH_TYPE 3529
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#define CONFIG_MXC_UART_BASE UART4_BASE
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#define CONSOLE_DEV "ttymxc3"
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/* USB Configs */
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#define CONFIG_USB_HOST_ETHER
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#define CONFIG_USB_ETHER_ASIX
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
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#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */
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#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
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#define CONFIG_MXC_USB_FLAGS 0
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#define CONFIG_PCA953X
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#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x30, 8}, {0x32, 8}, {0x34, 8} }
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#include "mx6sabre_common.h"
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/* Falcon Mode */
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#ifdef CONFIG_SPL_OS_BOOT
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#define CONFIG_SPL_FS_LOAD_ARGS_NAME "args"
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#define CONFIG_SPL_FS_LOAD_KERNEL_NAME "uImage"
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#define CONFIG_CMD_SPL
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#define CONFIG_SYS_SPL_ARGS_ADDR 0x18000000
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#define CONFIG_CMD_SPL_WRITE_SIZE (128 * SZ_1K)
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/* Falcon Mode - MMC support: args@1MB kernel@2MB */
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#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTOR 0x800 /* 1MB */
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#define CONFIG_SYS_MMCSD_RAW_MODE_ARGS_SECTORS (CONFIG_CMD_SPL_WRITE_SIZE / 512)
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#define CONFIG_SYS_MMCSD_RAW_MODE_KERNEL_SECTOR 0x1000 /* 2MB */
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#endif
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#ifdef CONFIG_MTD_NOR_FLASH
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#define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR
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#define CONFIG_SYS_FLASH_SECT_SIZE (128 * 1024)
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
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#define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
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#define CONFIG_FLASH_CFI_DRIVER /* Use drivers/cfi_flash.c */
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* Use buffered writes*/
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
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#endif
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#define CONFIG_SYS_FSL_USDHC_NUM 2
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#if defined(CONFIG_ENV_IS_IN_MMC)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#endif
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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#define CONFIG_SYS_I2C_SPEED 100000
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/* NAND stuff */
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#define CONFIG_NAND_MXS
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_SYS_NAND_BASE 0x40000000
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#define CONFIG_SYS_NAND_5_ADDR_CYCLE
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* DMA stuff, needed for GPMI/MXS NAND support */
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#define CONFIG_APBH_DMA
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#define CONFIG_APBH_DMA_BURST
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#define CONFIG_APBH_DMA_BURST8
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/* PMIC */
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#define CONFIG_POWER
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#define CONFIG_POWER_I2C
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#define CONFIG_POWER_PFUZE100
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#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
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#endif /* __MX6SABREAUTO_CONFIG_H */
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