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https://github.com/AsahiLinux/u-boot
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864ac2cf38
i.Core MX8M Plus is an EDIMM SoM based on NXP i.MX8M Plus from Engicam. i.Core MX8M Plus needs to mount on top of this Evaluation board for creating complete i.Core MX8M Plus EDIMM2.2 Starter Kit. Add support for it. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
73 lines
1.5 KiB
C
73 lines
1.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Engicam S.r.l.
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* Copyright (C) 2022 Amarula Solutions(India)
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*
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* Authors:
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* Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
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* Jagan Teki <jagan@amarulasolutions.com>
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <miiphy.h>
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#include <netdev.h>
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#include <linux/delay.h>
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#include <asm/global_data.h>
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#include <asm/mach-imx/iomux-v3.h>
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#include <asm-generic/gpio.h>
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#include <asm/arch/imx8mp_pins.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/mach-imx/gpio.h>
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DECLARE_GLOBAL_DATA_PTR;
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static void setup_fec(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* Enable RGMII TX clk output */
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setbits_le32(&gpr->gpr[1], BIT(22));
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}
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static int setup_eqos(void)
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{
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struct iomuxc_gpr_base_regs *gpr =
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(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
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/* set INTF as RGMII, enable RGMII TXC clock */
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clrsetbits_le32(&gpr->gpr[1],
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IOMUXC_GPR_GPR1_GPR_ENET_QOS_INTF_SEL_MASK, BIT(16));
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setbits_le32(&gpr->gpr[1], BIT(19) | BIT(21));
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return set_clk_eqos(ENET_125MHZ);
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}
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#if CONFIG_IS_ENABLED(NET)
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int board_init(void)
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{
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if (CONFIG_IS_ENABLED(FEC_MXC))
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setup_fec();
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if (CONFIG_IS_ENABLED(DWC_ETH_QOS))
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setup_eqos();
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return 0;
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}
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int board_late_init(void)
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{
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return 0;
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}
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