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The mysterious "Memory controller" PCI device which is present in PCI config space is improperly configured and crippled PCI Bridge which acts as PCIe Root Port for endpoint PCIe card. This PCI Bridge reports in PCI config space incorrect Class Code (Memory Controller) and incorrect Header Type (Type 0). It looks like HW bug in mvebu PCIe controller but apparently it can be changed via mvebu registers to correct values. The worst thing is that this PCI Bridge is crippled and its PCI config registers in range 0x10-0x34 alias access to internal mvebu registers which have different functionality as PCI Bridge registers. Moreover, configuration of PCI primary and secondary bus numbers (registers 0x18 and 0x19) is done via totally different mvebu registers via totally strange method and cannot be done via PCI Bridge config space. Due to above fact about PCI config range 0x10-0x34, allocate a private cfgcache[] buffer in the driver, to which PCI config access requests to the 0x10-0x34 space will be redirected in mvebu_pcie_read_config() and mvebu_pcie_write_config() functions. Function mvebu_pcie_write_config() will also catch writes to PCI_PRIMARY_BUS (0x18) and PCI_SECONDARY_BUS (0x19) registers and set PCI Bridge primary and secondary bus numbers via mvebu's own method. Also, Expansion ROM Base Address register (0x38) is available, but at different offset 0x30. So recalculate register offset before accessing PCI config space. After these steps U-Boot sees working PCI Bridge and CONFIG_PCI_PNP code can finally start enumerating all PCIe devices correctly, even with more complicated PCI topology. So update also mvebu_pcie_valid_addr() function to reflect state of the real device topology. Each PCIe port is de-facto isolated and every PCI Bridge which is part of PCIe Root Complex is also isolated, so put them on separate PCI buses as (local) device 0. U-Boot already supports enumerating separate PCI buses, real (HW) bus number can be retrieved by "PCI_BUS(bdf) - dev_seq(bus)" code, so update config read/write functions to properly handle more complicated tree topologies (e.g. when a PCIe switch with multiple PCI buses is connected to the PCIe port). Local bus number and local device number on mvebu are used for determining which config request type is used (Type 0 vs Type 1). On normal non-broken PCIe hardware it is done by primary and secondary bus numbers. So correctly translate settings between these numbers to ensure that correct config requests are sent over the PCIe bus. As bus numbers are correctly re-configured, it does not make sense to print some initial bogus configuration during probe, so remove this debug code. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de> |
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| .. | ||
| fsl_pci_init.c | ||
| Kconfig | ||
| Makefile | ||
| pci-aardvark.c | ||
| pci-emul-uclass.c | ||
| pci-rcar-gen2.c | ||
| pci-rcar-gen3.c | ||
| pci-uclass.c | ||
| pci_auto.c | ||
| pci_auto_common.c | ||
| pci_common.c | ||
| pci_compat.c | ||
| pci_gt64120.c | ||
| pci_internal.h | ||
| pci_mpc85xx.c | ||
| pci_msc01.c | ||
| pci_mvebu.c | ||
| pci_octeontx.c | ||
| pci_rom.c | ||
| pci_sandbox.c | ||
| pci_sh4.c | ||
| pci_sh7751.c | ||
| pci_sh7780.c | ||
| pci_tegra.c | ||
| pci_x86.c | ||
| pcie_brcmstb.c | ||
| pcie_dw_common.c | ||
| pcie_dw_common.h | ||
| pcie_dw_meson.c | ||
| pcie_dw_mvebu.c | ||
| pcie_dw_rockchip.c | ||
| pcie_dw_sifive.c | ||
| pcie_dw_ti.c | ||
| pcie_ecam_generic.c | ||
| pcie_ecam_synquacer.c | ||
| pcie_fsl.c | ||
| pcie_fsl.h | ||
| pcie_fsl_fixup.c | ||
| pcie_imx.c | ||
| pcie_intel_fpga.c | ||
| pcie_iproc.c | ||
| pcie_layerscape.c | ||
| pcie_layerscape.h | ||
| pcie_layerscape_ep.c | ||
| pcie_layerscape_fixup.c | ||
| pcie_layerscape_fixup_common.c | ||
| pcie_layerscape_fixup_common.h | ||
| pcie_layerscape_gen4.c | ||
| pcie_layerscape_gen4.h | ||
| pcie_layerscape_gen4_fixup.c | ||
| pcie_layerscape_rc.c | ||
| pcie_mediatek.c | ||
| pcie_octeon.c | ||
| pcie_phytium.c | ||
| pcie_rockchip.c | ||
| pcie_uniphier.c | ||
| pcie_xilinx.c | ||