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cd93d625fd
Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
216 lines
6.8 KiB
C
216 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Amlogic Meson Video Processing Unit driver
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*
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* Copyright (c) 2018 BayLibre, SAS.
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include "meson_vpu.h"
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/* OSDx_BLKx_CFG */
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#define OSD_CANVAS_SEL 16
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#define OSD_ENDIANNESS_LE BIT(15)
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#define OSD_ENDIANNESS_BE (0)
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#define OSD_BLK_MODE_422 (0x03 << 8)
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#define OSD_BLK_MODE_16 (0x04 << 8)
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#define OSD_BLK_MODE_32 (0x05 << 8)
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#define OSD_BLK_MODE_24 (0x07 << 8)
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#define OSD_OUTPUT_COLOR_RGB BIT(7)
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#define OSD_OUTPUT_COLOR_YUV (0)
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#define OSD_COLOR_MATRIX_32_RGBA (0x00 << 2)
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#define OSD_COLOR_MATRIX_32_ARGB (0x01 << 2)
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#define OSD_COLOR_MATRIX_32_ABGR (0x02 << 2)
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#define OSD_COLOR_MATRIX_32_BGRA (0x03 << 2)
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#define OSD_COLOR_MATRIX_24_RGB (0x00 << 2)
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#define OSD_COLOR_MATRIX_16_RGB655 (0x00 << 2)
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#define OSD_COLOR_MATRIX_16_RGB565 (0x04 << 2)
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#define OSD_INTERLACE_ENABLED BIT(1)
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#define OSD_INTERLACE_ODD BIT(0)
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#define OSD_INTERLACE_EVEN (0)
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/* OSDx_CTRL_STAT */
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#define OSD_ENABLE BIT(21)
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#define OSD_BLK0_ENABLE BIT(0)
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#define OSD_GLOBAL_ALPHA_SHIFT 12
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/* OSDx_CTRL_STAT2 */
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#define OSD_REPLACE_EN BIT(14)
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#define OSD_REPLACE_SHIFT 6
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/*
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* When the output is interlaced, the OSD must switch between
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* each field using the INTERLACE_SEL_ODD (0) of VIU_OSD1_BLK0_CFG_W0
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* at each vsync.
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* But the vertical scaler can provide such funtionnality if
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* is configured for 2:1 scaling with interlace options enabled.
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*/
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static void meson_vpp_setup_interlace_vscaler_osd1(struct meson_vpu_priv *priv,
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struct video_priv *uc_priv)
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{
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writel(BIT(3) /* Enable scaler */ |
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BIT(2), /* Select OSD1 */
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priv->io_base + _REG(VPP_OSD_SC_CTRL0));
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writel(((uc_priv->xsize - 1) << 16) | (uc_priv->ysize - 1),
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priv->io_base + _REG(VPP_OSD_SCI_WH_M1));
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/* 2:1 scaling */
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writel((0 << 16) | uc_priv->xsize,
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priv->io_base + _REG(VPP_OSD_SCO_H_START_END));
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writel(((0 >> 1) << 16) | (uc_priv->ysize >> 1),
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priv->io_base + _REG(VPP_OSD_SCO_V_START_END));
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/* 2:1 scaling values */
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writel(BIT(16), priv->io_base + _REG(VPP_OSD_VSC_INI_PHASE));
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writel(BIT(25), priv->io_base + _REG(VPP_OSD_VSC_PHASE_STEP));
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writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
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writel((4 << 0) /* osd_vsc_bank_length */ |
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(4 << 3) /* osd_vsc_top_ini_rcv_num0 */ |
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(1 << 8) /* osd_vsc_top_rpt_p0_num0 */ |
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(6 << 11) /* osd_vsc_bot_ini_rcv_num0 */ |
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(2 << 16) /* osd_vsc_bot_rpt_p0_num0 */ |
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BIT(23) /* osd_prog_interlace */ |
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BIT(24), /* Enable vertical scaler */
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priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
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}
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static void
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meson_vpp_disable_interlace_vscaler_osd1(struct meson_vpu_priv *priv)
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{
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writel(0, priv->io_base + _REG(VPP_OSD_SC_CTRL0));
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writel(0, priv->io_base + _REG(VPP_OSD_VSC_CTRL0));
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writel(0, priv->io_base + _REG(VPP_OSD_HSC_CTRL0));
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}
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void meson_vpu_setup_plane(struct udevice *dev, bool is_interlaced)
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{
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struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct meson_vpu_priv *priv = dev_get_priv(dev);
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u32 osd1_ctrl_stat;
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u32 osd1_blk0_cfg[5];
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bool osd1_interlace;
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unsigned int src_x1, src_x2, src_y1, src_y2;
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unsigned int dest_x1, dest_x2, dest_y1, dest_y2;
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dest_x1 = src_x1 = 0;
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dest_x2 = src_x2 = uc_priv->xsize;
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dest_y1 = src_y1 = 0;
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dest_y2 = src_y2 = uc_priv->ysize;
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
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/* VD1 Preblend vertical start/end */
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writel(FIELD_PREP(GENMASK(11, 0), 2303),
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priv->io_base + _REG(VPP_PREBLEND_VD1_V_START_END));
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/* Setup Blender */
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writel(uc_priv->xsize |
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uc_priv->ysize << 16,
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priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
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writel(0 << 16 |
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(uc_priv->xsize - 1),
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priv->io_base + _REG(VPP_OSD1_BLD_H_SCOPE));
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writel(0 << 16 |
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(uc_priv->ysize - 1),
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priv->io_base + _REG(VPP_OSD1_BLD_V_SCOPE));
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writel(uc_priv->xsize << 16 |
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uc_priv->ysize,
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priv->io_base + _REG(VPP_OUT_H_V_SIZE));
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} else {
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/* Enable VPP Postblend */
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writel(uc_priv->xsize,
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priv->io_base + _REG(VPP_POSTBLEND_H_SIZE));
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writel_bits(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE,
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priv->io_base + _REG(VPP_MISC));
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}
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/* uc_plat->base is the framebuffer */
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/* Enable OSD and BLK0, set max global alpha */
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osd1_ctrl_stat = OSD_ENABLE | (0xFF << OSD_GLOBAL_ALPHA_SHIFT) |
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OSD_BLK0_ENABLE;
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/* Set up BLK0 to point to the right canvas */
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osd1_blk0_cfg[0] = ((MESON_CANVAS_ID_OSD1 << OSD_CANVAS_SEL) |
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OSD_ENDIANNESS_LE);
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/* On GXBB, Use the old non-HDR RGB2YUV converter */
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_GXBB))
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osd1_blk0_cfg[0] |= OSD_OUTPUT_COLOR_RGB;
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/* For XRGB, replace the pixel's alpha by 0xFF */
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writel_bits(OSD_REPLACE_EN, OSD_REPLACE_EN,
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priv->io_base + _REG(VIU_OSD1_CTRL_STAT2));
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osd1_blk0_cfg[0] |= OSD_BLK_MODE_32 |
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OSD_COLOR_MATRIX_32_ARGB;
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if (is_interlaced) {
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osd1_interlace = true;
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dest_y1 /= 2;
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dest_y2 /= 2;
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} else {
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osd1_interlace = false;
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}
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/*
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* The format of these registers is (x2 << 16 | x1),
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* where x2 is exclusive.
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* e.g. +30x1920 would be (1919 << 16) | 30
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*/
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osd1_blk0_cfg[1] = ((src_x2 - 1) << 16) | src_x1;
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osd1_blk0_cfg[2] = ((src_y2 - 1) << 16) | src_y1;
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osd1_blk0_cfg[3] = ((dest_x2 - 1) << 16) | dest_x1;
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osd1_blk0_cfg[4] = ((dest_y2 - 1) << 16) | dest_y1;
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writel(osd1_ctrl_stat, priv->io_base + _REG(VIU_OSD1_CTRL_STAT));
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writel(osd1_blk0_cfg[0], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W0));
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writel(osd1_blk0_cfg[1], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W1));
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writel(osd1_blk0_cfg[2], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W2));
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writel(osd1_blk0_cfg[3], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W3));
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writel(osd1_blk0_cfg[4], priv->io_base + _REG(VIU_OSD1_BLK0_CFG_W4));
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/* If output is interlace, make use of the Scaler */
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if (osd1_interlace)
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meson_vpp_setup_interlace_vscaler_osd1(priv, uc_priv);
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else
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meson_vpp_disable_interlace_vscaler_osd1(priv);
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meson_canvas_setup(priv, MESON_CANVAS_ID_OSD1,
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uc_plat->base, uc_priv->xsize * 4,
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uc_priv->ysize, MESON_CANVAS_WRAP_NONE,
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MESON_CANVAS_BLKMODE_LINEAR);
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/* Enable OSD1 */
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if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
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writel(((dest_x2 - 1) << 16) | dest_x1,
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priv->io_base + _REG(VIU_OSD_BLEND_DIN0_SCOPE_H));
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writel(((dest_y2 - 1) << 16) | dest_y1,
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priv->io_base + _REG(VIU_OSD_BLEND_DIN0_SCOPE_V));
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writel(uc_priv->xsize << 16 | uc_priv->ysize,
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priv->io_base + _REG(VIU_OSD_BLEND_BLEND0_SIZE));
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writel(uc_priv->xsize << 16 | uc_priv->ysize,
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priv->io_base + _REG(VIU_OSD_BLEND_BLEND1_SIZE));
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writel_bits(3 << 8, 3 << 8,
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priv->io_base + _REG(OSD1_BLEND_SRC_CTRL));
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} else
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writel_bits(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND,
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priv->io_base + _REG(VPP_MISC));
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}
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