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PRCI module within SiFive SoC's has register with which we can reset the sub-systems within the SoC. The resets to DDR and ethernet sub systems within FU540-C000 SoC are active low, and are hold low by default on power-up. Currently these are directly asserted within prci driver via register read/write. With the DM based reset driver support here, we bind the reset driver with clock (prci) driver and assert the reset signals of both sub-system's appropriately. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> Reviewed-by: Pragnesh Patel <Pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
118 lines
2.5 KiB
C
118 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2020 Sifive, Inc.
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* Author: Sagar Kadam <sagar.kadam@sifive.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <reset-uclass.h>
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#include <asm/io.h>
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#include <dm/device_compat.h>
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#include <dm/lists.h>
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#include <linux/bitops.h>
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#define PRCI_RESETREG_OFFSET 0x28
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struct sifive_reset_priv {
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void *base;
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/* number of reset signals */
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int nr_reset;
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};
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static int sifive_rst_trigger(struct reset_ctl *rst, bool level)
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{
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struct sifive_reset_priv *priv = dev_get_priv(rst->dev);
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int id = rst->id;
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int regval = readl(priv->base + PRCI_RESETREG_OFFSET);
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/* Derive bitposition from rst id */
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if (level)
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/* Reset deassert */
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regval |= BIT(id);
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else
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/* Reset assert */
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regval &= ~BIT(id);
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writel(regval, priv->base + PRCI_RESETREG_OFFSET);
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return 0;
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}
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static int sifive_reset_assert(struct reset_ctl *rst)
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{
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return sifive_rst_trigger(rst, false);
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}
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static int sifive_reset_deassert(struct reset_ctl *rst)
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{
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return sifive_rst_trigger(rst, true);
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}
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static int sifive_reset_request(struct reset_ctl *rst)
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{
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struct sifive_reset_priv *priv = dev_get_priv(rst->dev);
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debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__,
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rst, rst->dev, rst->id, priv->nr_reset);
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if (rst->id > priv->nr_reset)
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return -EINVAL;
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return 0;
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}
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static int sifive_reset_free(struct reset_ctl *rst)
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{
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struct sifive_reset_priv *priv = dev_get_priv(rst->dev);
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debug("%s(rst=%p) (dev=%p, id=%lu) (nr_reset=%d)\n", __func__,
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rst, rst->dev, rst->id, priv->nr_reset);
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return 0;
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}
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static int sifive_reset_probe(struct udevice *dev)
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{
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struct sifive_reset_priv *priv = dev_get_priv(dev);
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priv->base = dev_remap_addr(dev);
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if (!priv->base)
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return -ENOMEM;
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return 0;
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}
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int sifive_reset_bind(struct udevice *dev, ulong count)
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{
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struct udevice *rst_dev;
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struct sifive_reset_priv *priv;
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int ret;
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ret = device_bind_driver_to_node(dev, "sifive-reset", "reset",
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dev_ofnode(dev), &rst_dev);
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if (ret) {
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dev_err(dev, "failed to bind sifive_reset driver (ret=%d)\n", ret);
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return ret;
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}
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priv = malloc(sizeof(struct sifive_reset_priv));
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priv->nr_reset = count;
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rst_dev->priv = priv;
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return 0;
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}
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const struct reset_ops sifive_reset_ops = {
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.request = sifive_reset_request,
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.rfree = sifive_reset_free,
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.rst_assert = sifive_reset_assert,
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.rst_deassert = sifive_reset_deassert,
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};
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U_BOOT_DRIVER(sifive_reset) = {
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.name = "sifive-reset",
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.id = UCLASS_RESET,
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.ops = &sifive_reset_ops,
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.probe = sifive_reset_probe,
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.priv_auto_alloc_size = sizeof(struct sifive_reset_priv),
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};
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