mirror of
https://github.com/AsahiLinux/u-boot
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a06752e36b
- Added I2C support for ML300.
- Added support for ML300 to read out its environment information
stored on the EEPROM.
- Added support to use board specific parameters as part of
U-Boot's environment information.
- Updated MLD files to support configuration for new features
above.
* Patches by Travis Sawyer, 5 Aug 2004:
- Remove incorrect bridge settings for eth group 6
- Add call to setup bridge in ppc_440x_eth_initialize
- Fix ppc_440x_eth_init to reset the phy only if its the
first time through, otherwise, just check the phy for the
autonegotiated speed/duplex. This allows the use of netconsole
- only print the speed/duplex the first time the phy is reset.
331 lines
14 KiB
C
331 lines
14 KiB
C
/* $Id: xipif_v1_23_b.c,v 1.1 2002/03/18 23:24:52 linnj Exp $ */
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/******************************************************************************
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*
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* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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* AS A COURTESY TO YOU, SOLELY FOR USE IN DEVELOPING PROGRAMS AND
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* SOLUTIONS FOR XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE,
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* OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
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* APPLICATION OR STANDARD, XILINX IS MAKING NO REPRESENTATION
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* THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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* AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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* FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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* WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE.
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*
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* (c) Copyright 2002 Xilinx Inc.
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* All rights reserved.
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*
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******************************************************************************/
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/******************************************************************************
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*
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* FILENAME:
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*
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* xipif.c
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*
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* DESCRIPTION:
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*
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* This file contains the implementation of the XIpIf component. The
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* XIpIf component encapsulates the IPIF, which is the standard interface
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* that IP must adhere to when connecting to a bus. The purpose of this
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* component is to encapsulate the IPIF processing such that maintainability
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* is increased. This component does not provide a lot of abstraction from
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* from the details of the IPIF as it is considered a building block for
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* device drivers. A device driver designer must be familiar with the
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* details of the IPIF hardware to use this component.
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*
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* The IPIF hardware provides a building block for all hardware devices such
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* that each device does not need to reimplement these building blocks. The
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* IPIF contains other building blocks, such as FIFOs and DMA channels, which
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* are also common to many devices. These blocks are implemented as separate
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* hardware blocks and instantiated within the IPIF. The primary hardware of
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* the IPIF which is implemented by this software component is the interrupt
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* architecture. Since there are many blocks of a device which may generate
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* interrupts, all the interrupt processing is contained in the common part
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* of the device, the IPIF. This interrupt processing is for the device level
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* only and does not include any processing for the interrupt controller.
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*
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* A device is a mechanism such as an Ethernet MAC. The device is made
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* up of several parts which include an IPIF and the IP. The IPIF contains most
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* of the device infrastructure which is common to all devices, such as
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* interrupt processing, DMA channels, and FIFOs. The infrastructure may also
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* be referred to as IPIF internal blocks since they are part of the IPIF and
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* are separate blocks that can be selected based upon the needs of the device.
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* The IP of the device is the logic that is unique to the device and interfaces
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* to the IPIF of the device.
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*
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* In general, there are two levels of registers within the IPIF. The first
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* level, referred to as the device level, contains registers which are for the
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* entire device. The second level, referred to as the IP level, contains
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* registers which are specific to the IP of the device. The two levels of
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* registers are designed to be hierarchical such that the device level is
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* is a more general register set above the more specific registers of the IP.
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* The IP level of registers provides functionality which is typically common
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* across all devices and allows IP designers to focus on the unique aspects
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* of the IP.
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*
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* The interrupt registers of the IPIF are parameterizable such that the only
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* the number of bits necessary for the device are implemented. The functions
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* of this component do not attempt to validate that the passed in arguments are
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* valid based upon the number of implemented bits. This is necessary to
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* maintain the level of performance required for the common components. Bits
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* of the registers are assigned starting at the least significant bit of the
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* registers.
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*
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* Critical Sections
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*
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* It is the responsibility of the device driver designer to use critical
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* sections as necessary when calling functions of the IPIF. This component
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* does not use critical sections and it does access registers using
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* read-modify-write operations. Calls to IPIF functions from a main thread
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* and from an interrupt context could produce unpredictable behavior such that
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* the caller must provide the appropriate critical sections.
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*
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* Mutual Exclusion
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*
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* The functions of the IPIF are not thread safe such that the caller of all
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* functions is responsible for ensuring mutual exclusion for an IPIF. Mutual
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* exclusion across multiple IPIF components is not necessary.
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*
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* NOTES:
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*
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* None.
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*
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* MODIFICATION HISTORY:
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*
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* Ver Who Date Changes
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* ----- ---- -------- -----------------------------------------------
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* 1.23b jhl 02/27/01 Repartioned to reduce size
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*
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******************************************************************************/
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/***************************** Include Files *********************************/
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#include "xipif_v1_23_b.h"
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#include "xio.h"
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/************************** Constant Definitions *****************************/
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/* the following constant is used to generate bit masks for register testing
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* in the self test functions, it defines the starting bit mask that is to be
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* shifted from the LSB to MSB in creating a register test mask
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*/
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#define XIIF_V123B_FIRST_BIT_MASK 1UL
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/**************************** Type Definitions *******************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/************************** Variable Definitions *****************************/
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/************************** Function Prototypes ******************************/
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static XStatus IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth);
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/******************************************************************************
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*
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* FUNCTION:
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*
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* XIpIf_SelfTest
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*
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* DESCRIPTION:
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*
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* This function performs a self test on the specified IPIF component. Many
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* of the registers in the IPIF are tested to ensure proper operation. This
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* function is destructive because the IPIF is reset at the start of the test
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* and at the end of the test to ensure predictable results. The IPIF reset
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* also resets the entire device that uses the IPIF. This function exits with
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* all interrupts for the device disabled.
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*
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* ARGUMENTS:
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*
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* InstancePtr points to the XIpIf to operate on.
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*
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* DeviceRegistersWidth contains the number of bits in the device interrupt
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* registers. The hardware is parameterizable such that only the number of bits
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* necessary to support a device are implemented. This value must be between 0
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* and 32 with 0 indicating there are no device interrupt registers used.
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*
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* IpRegistersWidth contains the number of bits in the IP interrupt registers
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* of the device. The hardware is parameterizable such that only the number of
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* bits necessary to support a device are implemented. This value must be
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* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
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*
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* RETURN VALUE:
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*
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* A value of XST_SUCCESS indicates the test was successful with no errors.
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* Any one of the following error values may also be returned.
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*
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* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was
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* not valid
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* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status
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* register did not read back correctly
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* XST_IPIF_IP_ACK_ERROR One or more bits in the IP interrupt
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* status register did not reset when acked
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* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register
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* did not read back correctly based upon
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* what was written to it
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*
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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/* the following constant defines the maximum number of bits which may be
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* used in the registers at the device and IP levels, this is based upon the
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* number of bits available in the registers
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*/
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#define XIIF_V123B_MAX_REG_BIT_COUNT 32
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XStatus
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XIpIfV123b_SelfTest(u32 RegBaseAddress, u8 IpRegistersWidth)
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{
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XStatus Status;
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/* assert to verify arguments are valid */
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XASSERT_NONVOID(IpRegistersWidth <= XIIF_V123B_MAX_REG_BIT_COUNT);
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/* reset the IPIF such that it's in a known state before the test
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* and interrupts are globally disabled
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*/
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XIIF_V123B_RESET(RegBaseAddress);
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/* perform the self test on the IP interrupt registers, if
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* it is not successful exit with the status
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*/
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Status = IpIntrSelfTest(RegBaseAddress, IpRegistersWidth);
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if (Status != XST_SUCCESS) {
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return Status;
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}
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/* reset the IPIF such that it's in a known state before exiting test */
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XIIF_V123B_RESET(RegBaseAddress);
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/* reaching this point means there were no errors, return success */
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return XST_SUCCESS;
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}
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/******************************************************************************
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*
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* FUNCTION:
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*
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* IpIntrSelfTest
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*
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* DESCRIPTION:
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*
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* Perform a self test on the IP interrupt registers of the IPIF. This
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* function modifies registers of the IPIF such that they are not guaranteed
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* to be in the same state when it returns. Any bits in the IP interrupt
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* status register which are set are assumed to be set by default after a reset
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* and are not tested in the test.
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*
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* ARGUMENTS:
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*
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* InstancePtr points to the XIpIf to operate on.
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*
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* IpRegistersWidth contains the number of bits in the IP interrupt registers
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* of the device. The hardware is parameterizable such that only the number of
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* bits necessary to support a device are implemented. This value must be
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* between 0 and 32 with 0 indicating there are no IP interrupt registers used.
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*
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* RETURN VALUE:
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*
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* A status indicating XST_SUCCESS if the test was successful. Otherwise, one
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* of the following values is returned.
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*
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* XST_IPIF_RESET_REGISTER_ERROR The value of a register at reset was
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* not valid
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* XST_IPIF_IP_STATUS_ERROR A write to the IP interrupt status
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* register did not read back correctly
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* XST_IPIF_IP_ACK_ERROR One or more bits in the IP status
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* register did not reset when acked
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* XST_IPIF_IP_ENABLE_ERROR The IP interrupt enable register
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* did not read back correctly based upon
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* what was written to it
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* NOTES:
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*
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* None.
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*
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******************************************************************************/
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static XStatus
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IpIntrSelfTest(u32 RegBaseAddress, u32 IpRegistersWidth)
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{
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/* ensure that the IP interrupt interrupt enable register is zero
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* as it should be at reset, the interrupt status is dependent upon the
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* IP such that it's reset value is not known
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*/
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if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
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return XST_IPIF_RESET_REGISTER_ERROR;
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}
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/* if there are any used IP interrupts, then test all of the interrupt
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* bits in all testable registers
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*/
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if (IpRegistersWidth > 0) {
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u32 BitCount;
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u32 IpInterruptMask = XIIF_V123B_FIRST_BIT_MASK;
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u32 Mask = XIIF_V123B_FIRST_BIT_MASK; /* bits assigned MSB to LSB */
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u32 InterruptStatus;
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/* generate the register masks to be used for IP register tests, the
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* number of bits supported by the hardware is parameterizable such
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* that only that number of bits are implemented in the registers, the
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* bits are allocated starting at the MSB of the registers
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*/
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for (BitCount = 1; BitCount < IpRegistersWidth; BitCount++) {
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Mask = Mask << 1;
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IpInterruptMask |= Mask;
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}
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/* get the current IP interrupt status register contents, any bits
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* already set must default to 1 at reset in the device and these
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* bits can't be tested in the following test, remove these bits from
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* the mask that was generated for the test
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*/
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InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
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IpInterruptMask &= ~InterruptStatus;
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/* set the bits in the device status register and verify them by reading
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* the register again, all bits of the register are latched
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*/
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XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
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InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
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if ((InterruptStatus & IpInterruptMask) != IpInterruptMask)
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{
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return XST_IPIF_IP_STATUS_ERROR;
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}
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/* test to ensure that the bits set in the IP interrupt status register
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* can be cleared by acknowledging them in the IP interrupt status
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* register then read it again and verify it was cleared
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*/
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XIIF_V123B_WRITE_IISR(RegBaseAddress, IpInterruptMask);
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InterruptStatus = XIIF_V123B_READ_IISR(RegBaseAddress);
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if ((InterruptStatus & IpInterruptMask) != 0) {
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return XST_IPIF_IP_ACK_ERROR;
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}
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/* set the IP interrupt enable set register and then read the IP
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* interrupt enable register and verify the interrupts were enabled
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*/
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XIIF_V123B_WRITE_IIER(RegBaseAddress, IpInterruptMask);
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if (XIIF_V123B_READ_IIER(RegBaseAddress) != IpInterruptMask) {
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return XST_IPIF_IP_ENABLE_ERROR;
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}
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/* clear the IP interrupt enable register and then read the
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* IP interrupt enable register and verify the interrupts were disabled
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*/
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XIIF_V123B_WRITE_IIER(RegBaseAddress, 0);
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if (XIIF_V123B_READ_IIER(RegBaseAddress) != 0) {
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return XST_IPIF_IP_ENABLE_ERROR;
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}
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}
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return XST_SUCCESS;
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}
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