mirror of
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a4814a69d3
commit 0edf8b5b2f breaks
building on a different directory with the O= parameter.
The patch wil fix this issue, generating always asm-offsets.h before
the other targets.
Signed-off-by: Stefano Babic <sbabic@denx.de>
CC: Matthias Weisser <weisserm@arcor.de>
CC: Wolfgang Denk <wd@denx.de>
364 lines
8.1 KiB
ArmAsm
364 lines
8.1 KiB
ArmAsm
/*
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* Copyright (C) 2007, Guennadi Liakhovetski <lg@denx.de>
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*
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* (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/arch/imx-regs.h>
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#include <generated/asm-offsets.h>
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#include "mx35pdk.h"
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/*
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* return soc version
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* 0x10: TO1
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* 0x20: TO2
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* 0x30: TO3
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*/
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.macro check_soc_version ret, tmp
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ldr \tmp, =IIM_BASE_ADDR
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ldr \ret, [\tmp, #IIM_SREV]
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cmp \ret, #0x00
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moveq \tmp, #ROMPATCH_REV
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ldreq \ret, [\tmp]
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moveq \ret, \ret, lsl #4
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addne \ret, \ret, #0x10
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.endm
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/*
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* AIPS setup - Only setup MPROTx registers.
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* The PACR default values are good.
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*/
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.macro init_aips
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/*
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* Set all MPROTx to be non-bufferable, trusted for R/W,
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* not forced to user-mode.
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*/
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =AIPS_MPR_CONFIG
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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ldr r0, =AIPS2_BASE_ADDR
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str r1, [r0, #0x00]
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str r1, [r0, #0x04]
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/*
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* Clear the on and off peripheral modules Supervisor Protect bit
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* for SDMA to access them. Did not change the AIPS control registers
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* (offset 0x20) access type
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*/
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ldr r0, =AIPS1_BASE_ADDR
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ldr r1, =AIPS_OPACR_CONFIG
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str r1, [r0, #0x40]
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str r1, [r0, #0x44]
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str r1, [r0, #0x48]
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str r1, [r0, #0x4C]
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str r1, [r0, #0x50]
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ldr r0, =AIPS2_BASE_ADDR
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str r1, [r0, #0x40]
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str r1, [r0, #0x44]
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str r1, [r0, #0x48]
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str r1, [r0, #0x4C]
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str r1, [r0, #0x50]
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.endm
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/* MAX (Multi-Layer AHB Crossbar Switch) setup */
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.macro init_max
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ldr r0, =MAX_BASE_ADDR
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/* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */
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ldr r1, =MAX_MPR_CONFIG
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str r1, [r0, #0x000] /* for S0 */
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str r1, [r0, #0x100] /* for S1 */
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str r1, [r0, #0x200] /* for S2 */
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str r1, [r0, #0x300] /* for S3 */
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str r1, [r0, #0x400] /* for S4 */
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/* SGPCR - always park on last master */
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ldr r1, =MAX_SGPCR_CONFIG
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str r1, [r0, #0x010] /* for S0 */
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str r1, [r0, #0x110] /* for S1 */
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str r1, [r0, #0x210] /* for S2 */
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str r1, [r0, #0x310] /* for S3 */
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str r1, [r0, #0x410] /* for S4 */
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/* MGPCR - restore default values */
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ldr r1, =MAX_MGPCR_CONFIG
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str r1, [r0, #0x800] /* for M0 */
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str r1, [r0, #0x900] /* for M1 */
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str r1, [r0, #0xA00] /* for M2 */
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str r1, [r0, #0xB00] /* for M3 */
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str r1, [r0, #0xC00] /* for M4 */
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str r1, [r0, #0xD00] /* for M5 */
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.endm
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/* M3IF setup */
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.macro init_m3if
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/* Configure M3IF registers */
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ldr r1, =M3IF_BASE_ADDR
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/*
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* M3IF Control Register (M3IFCTL)
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* MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000
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* MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000
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* MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000
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* MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
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* MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
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* MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
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* MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040
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* MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000
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* ------------
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* 0x00000040
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*/
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ldr r0, =M3IF_CONFIG
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str r0, [r1] /* M3IF control reg */
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.endm
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/* CPLD on CS5 setup */
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.macro init_debug_board
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ldr r0, =DBG_BASE_ADDR
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ldr r1, =DBG_CSCR_U_CONFIG
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str r1, [r0, #0x00]
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ldr r1, =DBG_CSCR_L_CONFIG
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str r1, [r0, #0x04]
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ldr r1, =DBG_CSCR_A_CONFIG
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str r1, [r0, #0x08]
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.endm
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/* clock setup */
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.macro init_clock
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ldr r0, =CCM_BASE_ADDR
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/* default CLKO to 1/32 of the ARM core*/
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ldr r1, [r0, #CLKCTL_COSR]
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bic r1, r1, #0x00000FF00
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bic r1, r1, #0x0000000FF
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mov r2, #0x00006C00
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add r2, r2, #0x67
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orr r1, r1, r2
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str r1, [r0, #CLKCTL_COSR]
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ldr r2, =CCM_CCMR_CONFIG
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str r2, [r0, #CLKCTL_CCMR]
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check_soc_version r1, r2
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cmp r1, #CHIP_REV_2_0
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ldrhs r3, =CCM_MPLL_532_HZ
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bhs 1f
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ldr r2, [r0, #CLKCTL_PDR0]
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tst r2, #CLKMODE_CONSUMER
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ldrne r3, =CCM_MPLL_532_HZ /* consumer path*/
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ldreq r3, =CCM_MPLL_399_HZ /* auto path*/
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1:
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str r3, [r0, #CLKCTL_MPCTL]
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ldr r1, =CCM_PPLL_300_HZ
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str r1, [r0, #CLKCTL_PPCTL]
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ldr r1, =CCM_PDR0_CONFIG
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bic r1, r1, #0x800000
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str r1, [r0, #CLKCTL_PDR0]
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ldr r1, [r0, #CLKCTL_CGR0]
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orr r1, r1, #0x0C300000
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str r1, [r0, #CLKCTL_CGR0]
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ldr r1, [r0, #CLKCTL_CGR1]
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orr r1, r1, #0x00000C00
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orr r1, r1, #0x00000003
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str r1, [r0, #CLKCTL_CGR1]
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.endm
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.macro setup_sdram
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ldr r0, =ESDCTL_BASE_ADDR
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mov r3, #0x2000
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str r3, [r0, #0x0]
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str r3, [r0, #0x8]
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/*ip(r12) has used to save lr register in upper calling*/
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mov fp, lr
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mov r5, #0x00
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mov r2, #0x00
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mov r1, #CSD0_BASE_ADDR
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bl setup_sdram_bank
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mov r5, #0x00
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mov r2, #0x00
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mov r1, #CSD1_BASE_ADDR
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bl setup_sdram_bank
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mov lr, fp
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1:
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ldr r3, =ESDCTL_DELAY_LINE5
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str r3, [r0, #0x30]
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.endm
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.globl lowlevel_init
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lowlevel_init:
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mov r10, lr
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mrc 15, 0, r1, c1, c0, 0
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mrc 15, 0, r0, c1, c0, 1
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orr r0, r0, #7
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mcr 15, 0, r0, c1, c0, 1
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orr r1, r1, #(1<<11)
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/* Set unaligned access enable */
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orr r1, r1, #(1<<22)
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/* Set low int latency enable */
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orr r1, r1, #(1<<21)
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mcr 15, 0, r1, c1, c0, 0
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mov r0, #0
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/* Set branch prediction enable */
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mcr 15, 0, r0, c15, c2, 4
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mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
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mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
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mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
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/*
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* initializes very early AIPS
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* Then it also initializes Multi-Layer AHB Crossbar Switch,
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* M3IF
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* Also setup the Peripheral Port Remap register inside the core
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*/
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ldr r0, =0x40000015 /* start from AIPS 2GB region */
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mcr p15, 0, r0, c15, c2, 4
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init_aips
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init_max
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init_m3if
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init_clock
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init_debug_board
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cmp pc, #PHYS_SDRAM_1
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blo init_sdram_start
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cmp pc, #(PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)
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blo skip_sdram_setup
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init_sdram_start:
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/*init_sdram*/
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setup_sdram
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skip_sdram_setup:
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mov lr, r10
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mov pc, lr
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/*
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* r0: ESDCTL control base, r1: sdram slot base
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* r2: DDR type(0:DDR2, 1:MDDR) r3, r4:working base
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*/
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setup_sdram_bank:
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mov r3, #0xE
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tst r2, #0x1
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orreq r3, r3, #0x300 /*DDR2*/
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str r3, [r0, #0x10]
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bic r3, r3, #0x00A
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str r3, [r0, #0x10]
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beq 2f
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mov r3, #0x20000
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1: subs r3, r3, #1
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bne 1b
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2: tst r2, #0x1
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ldreq r3, =ESDCTL_DDR2_CONFIG
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ldrne r3, =ESDCTL_MDDR_CONFIG
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cmp r1, #CSD1_BASE_ADDR
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strlo r3, [r0, #0x4]
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strhs r3, [r0, #0xC]
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ldr r3, =ESDCTL_0x92220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, =ESDCTL_PRECHARGE
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strb r3, [r1, r4]
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tst r2, #0x1
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bne skip_set_mode
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cmp r1, #CSD1_BASE_ADDR
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ldr r3, =ESDCTL_0xB2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, =ESDCTL_DDR2_EMR2
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strb r3, [r1, r4]
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ldr r4, =ESDCTL_DDR2_EMR3
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strb r3, [r1, r4]
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ldr r4, =ESDCTL_DDR2_EN_DLL
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strb r3, [r1, r4]
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ldr r4, =ESDCTL_DDR2_RESET_DLL
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strb r3, [r1, r4]
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ldr r3, =ESDCTL_0x92220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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ldr r4, =ESDCTL_PRECHARGE
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strb r3, [r1, r4]
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skip_set_mode:
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cmp r1, #CSD1_BASE_ADDR
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ldr r3, =ESDCTL_0xA2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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mov r3, #0xDA
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strb r3, [r1]
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strb r3, [r1]
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ldr r3, =ESDCTL_0xB2220000
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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tst r2, #0x1
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ldreq r4, =ESDCTL_DDR2_MR
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ldrne r4, =ESDCTL_MDDR_MR
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mov r3, #0xDA
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strb r3, [r1, r4]
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ldreq r4, =ESDCTL_DDR2_OCD_DEFAULT
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streqb r3, [r1, r4]
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ldreq r4, =ESDCTL_DDR2_EN_DLL
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ldrne r4, =ESDCTL_MDDR_EMR
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strb r3, [r1, r4]
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cmp r1, #CSD1_BASE_ADDR
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ldr r3, =ESDCTL_0x82228080
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strlo r3, [r0, #0x0]
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strhs r3, [r0, #0x8]
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tst r2, #0x1
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moveq r4, #0x20000
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movne r4, #0x200
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1: subs r4, r4, #1
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bne 1b
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str r3, [r1, #0x100]
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ldr r4, [r1, #0x100]
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cmp r3, r4
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movne r3, #1
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moveq r3, #0
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mov pc, lr
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