mirror of
https://github.com/AsahiLinux/u-boot
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436 lines
12 KiB
C
436 lines
12 KiB
C
/*
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* (C) Copyright 2006-2008
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* Texas Instruments, <www.ti.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _CPU_H
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#define _CPU_H
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/* Register offsets of common modules */
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/* Control */
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#ifndef __ASSEMBLY__
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typedef struct ctrl {
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unsigned char res1[0xC0];
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unsigned short gpmc_nadv_ale; /* 0xC0 */
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unsigned short gpmc_noe; /* 0xC2 */
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unsigned short gpmc_nwe; /* 0xC4 */
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unsigned char res2[0x22A];
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unsigned int status; /* 0x2F0 */
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unsigned int gpstatus; /* 0x2F4 */
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unsigned char res3[0x08];
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unsigned int rpubkey_0; /* 0x300 */
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unsigned int rpubkey_1; /* 0x304 */
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unsigned int rpubkey_2; /* 0x308 */
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unsigned int rpubkey_3; /* 0x30C */
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unsigned int rpubkey_4; /* 0x310 */
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unsigned char res4[0x04];
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unsigned int randkey_0; /* 0x318 */
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unsigned int randkey_1; /* 0x31C */
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unsigned int randkey_2; /* 0x320 */
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unsigned int randkey_3; /* 0x324 */
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unsigned char res5[0x124];
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unsigned int ctrl_omap_stat; /* 0x44C */
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} ctrl_t;
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#else /* __ASSEMBLY__ */
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#define CONTROL_STATUS 0x2F0
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#endif /* __ASSEMBLY__ */
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/* cpu type */
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#define OMAP3503 0x5c00
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#define OMAP3515 0x1c00
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#define OMAP3525 0x4c00
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#define OMAP3530 0x0c00
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#ifndef __ASSEMBLY__
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typedef struct ctrl_id {
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unsigned char res1[0x4];
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unsigned int idcode; /* 0x04 */
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unsigned int prod_id; /* 0x08 */
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unsigned char res2[0x0C];
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unsigned int die_id_0; /* 0x18 */
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unsigned int die_id_1; /* 0x1C */
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unsigned int die_id_2; /* 0x20 */
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unsigned int die_id_3; /* 0x24 */
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} ctrl_id_t;
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#endif /* __ASSEMBLY__ */
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/* device type */
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#define DEVICE_MASK (0x7 << 8)
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#define SYSBOOT_MASK 0x1F
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#define TST_DEVICE 0x0
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#define EMU_DEVICE 0x1
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#define HS_DEVICE 0x2
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#define GP_DEVICE 0x3
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/* GPMC CS3/cs4/cs6 not avaliable */
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#define GPMC_BASE (OMAP34XX_GPMC_BASE)
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#define GPMC_CONFIG_CS0 0x60
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#define GPMC_CONFIG_CS5 0x150
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#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
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#define GPMC_CONFIG_CS5_BASE (GPMC_BASE + GPMC_CONFIG_CS5)
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#define GPMC_CONFIG_WP 0x10
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#define GPMC_CONFIG_WIDTH 0x30
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#ifndef __ASSEMBLY__
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typedef struct gpmc {
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned char res2[0x4];
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unsigned int irqstatus; /* 0x18 */
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unsigned int irqenable; /* 0x1C */
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unsigned char res3[0x20];
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unsigned int timeout_control; /* 0x40 */
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unsigned char res4[0xC];
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unsigned int config; /* 0x50 */
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unsigned int status; /* 0x54 */
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unsigned char res5[0x19C];
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unsigned int ecc_config; /* 0x1F4 */
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unsigned int ecc_control; /* 0x1F8 */
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unsigned int ecc_size_config; /* 0x1FC */
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unsigned int ecc1_result; /* 0x200 */
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unsigned int ecc2_result; /* 0x204 */
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unsigned int ecc3_result; /* 0x208 */
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unsigned int ecc4_result; /* 0x20C */
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unsigned int ecc5_result; /* 0x210 */
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unsigned int ecc6_result; /* 0x214 */
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unsigned int ecc7_result; /* 0x218 */
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unsigned int ecc8_result; /* 0x21C */
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unsigned int ecc9_result; /* 0x220 */
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} gpmc_t;
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typedef struct gpmc_csx {
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unsigned int config1; /* 0x00 */
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unsigned int config2; /* 0x04 */
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unsigned int config3; /* 0x08 */
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unsigned int config4; /* 0x0C */
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unsigned int config5; /* 0x10 */
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unsigned int config6; /* 0x14 */
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unsigned int config7; /* 0x18 */
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unsigned int nand_cmd; /* 0x1C */
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unsigned int nand_adr; /* 0x20 */
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unsigned int nand_dat; /* 0x24 */
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} gpmc_csx_t;
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#else /* __ASSEMBLY__ */
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#define GPMC_CONFIG1 0x00
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#define GPMC_CONFIG2 0x04
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#define GPMC_CONFIG3 0x08
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#define GPMC_CONFIG4 0x0C
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#define GPMC_CONFIG5 0x10
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#define GPMC_CONFIG6 0x14
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#define GPMC_CONFIG7 0x18
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#endif /* __ASSEMBLY__ */
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/* GPMC Mapping */
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#define FLASH_BASE 0x10000000 /* NOR flash, */
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/* aligned to 256 Meg */
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#define FLASH_BASE_SDPV1 0x04000000 /* NOR flash, */
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/* aligned to 64 Meg */
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#define FLASH_BASE_SDPV2 0x10000000 /* NOR flash, */
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/* aligned to 256 Meg */
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#define DEBUG_BASE 0x08000000 /* debug board */
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#define NAND_BASE 0x30000000 /* NAND addr */
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/* (actual size small port) */
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#define PISMO2_BASE 0x18000000 /* PISMO2 CS1/2 */
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#define ONENAND_MAP 0x20000000 /* OneNand addr */
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/* (actual size small port) */
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/* SMS */
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#ifndef __ASSEMBLY__
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typedef struct sms {
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned char res2[0x34];
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unsigned int rg_att0; /* 0x48 */
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unsigned char res3[0x84];
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unsigned int class_arb0; /* 0xD0 */
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} sms_t;
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#endif /* __ASSEMBLY__ */
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#define BURSTCOMPLETE_GROUP7 (0x1 << 31)
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/* SDRC */
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#ifndef __ASSEMBLY__
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typedef struct sdrc_cs {
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unsigned int mcfg; /* 0x80 || 0xB0 */
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unsigned int mr; /* 0x84 || 0xB4 */
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unsigned char res1[0x4];
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unsigned int emr2; /* 0x8C || 0xBC */
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unsigned char res2[0x14];
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unsigned int rfr_ctrl; /* 0x84 || 0xD4 */
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unsigned int manual; /* 0xA8 || 0xD8 */
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unsigned char res3[0x4];
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} sdrc_cs_t;
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typedef struct sdrc_actim {
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unsigned int ctrla; /* 0x9C || 0xC4 */
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unsigned int ctrlb; /* 0xA0 || 0xC8 */
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} sdrc_actim_t;
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typedef struct sdrc {
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unsigned char res1[0x10];
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unsigned int sysconfig; /* 0x10 */
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unsigned int status; /* 0x14 */
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unsigned char res2[0x28];
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unsigned int cs_cfg; /* 0x40 */
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unsigned int sharing; /* 0x44 */
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unsigned char res3[0x18];
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unsigned int dlla_ctrl; /* 0x60 */
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unsigned int dlla_status; /* 0x64 */
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unsigned int dllb_ctrl; /* 0x68 */
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unsigned int dllb_status; /* 0x6C */
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unsigned int power; /* 0x70 */
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unsigned char res4[0xC];
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sdrc_cs_t cs[2]; /* 0x80 || 0xB0 */
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} sdrc_t;
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#endif /* __ASSEMBLY__ */
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#define DLLPHASE_90 (0x1 << 1)
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#define LOADDLL (0x1 << 2)
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#define ENADLL (0x1 << 3)
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#define DLL_DELAY_MASK 0xFF00
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#define DLL_NO_FILTER_MASK ((0x1 << 9) | (0x1 << 8))
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#define PAGEPOLICY_HIGH (0x1 << 0)
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#define SRFRONRESET (0x1 << 7)
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#define WAKEUPPROC (0x1 << 26)
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#define DDR_SDRAM (0x1 << 0)
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#define DEEPPD (0x1 << 3)
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#define B32NOT16 (0x1 << 4)
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#define BANKALLOCATION (0x2 << 6)
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#define RAMSIZE_128 (0x40 << 8) /* RAM size in 2MB chunks */
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#define ADDRMUXLEGACY (0x1 << 19)
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#define CASWIDTH_10BITS (0x5 << 20)
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#define RASWIDTH_13BITS (0x2 << 24)
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#define BURSTLENGTH4 (0x2 << 0)
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#define CASL3 (0x3 << 4)
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#define SDRC_ACTIM_CTRL0_BASE (OMAP34XX_SDRC_BASE + 0x9C)
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#define SDRC_ACTIM_CTRL1_BASE (OMAP34XX_SDRC_BASE + 0xC4)
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#define ARE_ARCV_1 (0x1 << 0)
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#define ARCV (0x4e2 << 8) /* Autorefresh count */
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#define OMAP34XX_SDRC_CS0 0x80000000
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#define OMAP34XX_SDRC_CS1 0xA0000000
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#define CMD_NOP 0x0
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#define CMD_PRECHARGE 0x1
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#define CMD_AUTOREFRESH 0x2
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#define CMD_ENTR_PWRDOWN 0x3
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#define CMD_EXIT_PWRDOWN 0x4
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#define CMD_ENTR_SRFRSH 0x5
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#define CMD_CKE_HIGH 0x6
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#define CMD_CKE_LOW 0x7
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#define SOFTRESET (0x1 << 1)
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#define SMART_IDLE (0x2 << 3)
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#define REF_ON_IDLE (0x1 << 6)
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/* timer regs offsets (32 bit regs) */
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#ifndef __ASSEMBLY__
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typedef struct gptimer {
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unsigned int tidr; /* 0x00 r */
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unsigned char res[0xc];
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unsigned int tiocp_cfg; /* 0x10 rw */
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unsigned int tistat; /* 0x14 r */
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unsigned int tisr; /* 0x18 rw */
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unsigned int tier; /* 0x1c rw */
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unsigned int twer; /* 0x20 rw */
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unsigned int tclr; /* 0x24 rw */
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unsigned int tcrr; /* 0x28 rw */
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unsigned int tldr; /* 0x2c rw */
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unsigned int ttgr; /* 0x30 rw */
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unsigned int twpc; /* 0x34 r*/
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unsigned int tmar; /* 0x38 rw*/
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unsigned int tcar1; /* 0x3c r */
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unsigned int tcicr; /* 0x40 rw */
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unsigned int tcar2; /* 0x44 r */
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} gptimer_t;
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#endif /* __ASSEMBLY__ */
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/* enable sys_clk NO-prescale /1 */
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#define GPT_EN ((0x0 << 2) | (0x1 << 1) | (0x1 << 0))
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/* Watchdog */
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#ifndef __ASSEMBLY__
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typedef struct watchdog {
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unsigned char res1[0x34];
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unsigned int wwps; /* 0x34 r */
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unsigned char res2[0x10];
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unsigned int wspr; /* 0x48 rw */
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} watchdog_t;
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#endif /* __ASSEMBLY__ */
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#define WD_UNLOCK1 0xAAAA
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#define WD_UNLOCK2 0x5555
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/* PRCM */
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#define PRCM_BASE 0x48004000
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#ifndef __ASSEMBLY__
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typedef struct prcm {
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unsigned int fclken_iva2; /* 0x00 */
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unsigned int clken_pll_iva2; /* 0x04 */
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unsigned char res1[0x1c];
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unsigned int idlest_pll_iva2; /* 0x24 */
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unsigned char res2[0x18];
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unsigned int clksel1_pll_iva2 ; /* 0x40 */
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unsigned int clksel2_pll_iva2; /* 0x44 */
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unsigned char res3[0x8bc];
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unsigned int clken_pll_mpu; /* 0x904 */
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unsigned char res4[0x1c];
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unsigned int idlest_pll_mpu; /* 0x924 */
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unsigned char res5[0x18];
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unsigned int clksel1_pll_mpu; /* 0x940 */
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unsigned int clksel2_pll_mpu; /* 0x944 */
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unsigned char res6[0xb8];
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unsigned int fclken1_core; /* 0xa00 */
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unsigned char res7[0xc];
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unsigned int iclken1_core; /* 0xa10 */
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unsigned int iclken2_core; /* 0xa14 */
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unsigned char res8[0x28];
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unsigned int clksel_core; /* 0xa40 */
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unsigned char res9[0xbc];
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unsigned int fclken_gfx; /* 0xb00 */
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unsigned char res10[0xc];
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unsigned int iclken_gfx; /* 0xb10 */
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unsigned char res11[0x2c];
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unsigned int clksel_gfx; /* 0xb40 */
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unsigned char res12[0xbc];
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unsigned int fclken_wkup; /* 0xc00 */
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unsigned char res13[0xc];
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unsigned int iclken_wkup; /* 0xc10 */
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unsigned char res14[0xc];
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unsigned int idlest_wkup; /* 0xc20 */
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unsigned char res15[0x1c];
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unsigned int clksel_wkup; /* 0xc40 */
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unsigned char res16[0xbc];
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unsigned int clken_pll; /* 0xd00 */
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unsigned char res17[0x1c];
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unsigned int idlest_ckgen; /* 0xd20 */
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unsigned char res18[0x1c];
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unsigned int clksel1_pll; /* 0xd40 */
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unsigned int clksel2_pll; /* 0xd44 */
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unsigned int clksel3_pll; /* 0xd48 */
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unsigned char res19[0xb4];
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unsigned int fclken_dss; /* 0xe00 */
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unsigned char res20[0xc];
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unsigned int iclken_dss; /* 0xe10 */
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unsigned char res21[0x2c];
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unsigned int clksel_dss; /* 0xe40 */
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unsigned char res22[0xbc];
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unsigned int fclken_cam; /* 0xf00 */
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unsigned char res23[0xc];
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unsigned int iclken_cam; /* 0xf10 */
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unsigned char res24[0x2c];
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unsigned int clksel_cam; /* 0xf40 */
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unsigned char res25[0xbc];
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unsigned int fclken_per; /* 0x1000 */
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unsigned char res26[0xc];
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unsigned int iclken_per; /* 0x1010 */
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unsigned char res27[0x2c];
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unsigned int clksel_per; /* 0x1040 */
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unsigned char res28[0xfc];
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unsigned int clksel1_emu; /* 0x1140 */
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} prcm_t;
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#else /* __ASSEMBLY__ */
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#define CM_CLKSEL_CORE 0x48004a40
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#define CM_CLKSEL_GFX 0x48004b40
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#define CM_CLKSEL_WKUP 0x48004c40
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#define CM_CLKEN_PLL 0x48004d00
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#define CM_CLKSEL1_PLL 0x48004d40
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#define CM_CLKSEL1_EMU 0x48005140
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#endif /* __ASSEMBLY__ */
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#define PRM_BASE 0x48306000
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#ifndef __ASSEMBLY__
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typedef struct prm {
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unsigned char res1[0xd40];
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unsigned int clksel; /* 0xd40 */
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unsigned char res2[0x50c];
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unsigned int rstctrl; /* 0x1250 */
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unsigned char res3[0x1c];
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unsigned int clksrc_ctrl; /* 0x1270 */
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} prm_t;
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#else /* __ASSEMBLY__ */
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#define PRM_RSTCTRL 0x48307250
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#endif /* __ASSEMBLY__ */
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#define SYSCLKDIV_1 (0x1 << 6)
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#define SYSCLKDIV_2 (0x1 << 7)
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#define CLKSEL_GPT1 (0x1 << 0)
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#define EN_GPT1 (0x1 << 0)
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#define EN_32KSYNC (0x1 << 2)
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#define ST_WDT2 (0x1 << 5)
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#define ST_MPU_CLK (0x1 << 0)
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#define ST_CORE_CLK (0x1 << 0)
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#define ST_PERIPH_CLK (0x1 << 1)
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#define ST_IVA2_CLK (0x1 << 0)
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#define RESETDONE (0x1 << 0)
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#define TCLR_ST (0x1 << 0)
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#define TCLR_AR (0x1 << 1)
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#define TCLR_PRE (0x1 << 5)
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/* SMX-APE */
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#define PM_RT_APE_BASE_ADDR_ARM (SMX_APE_BASE + 0x10000)
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#define PM_GPMC_BASE_ADDR_ARM (SMX_APE_BASE + 0x12400)
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#define PM_OCM_RAM_BASE_ADDR_ARM (SMX_APE_BASE + 0x12800)
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#define PM_IVA2_BASE_ADDR_ARM (SMX_APE_BASE + 0x14000)
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#ifndef __ASSEMBLY__
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typedef struct pm {
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unsigned char res1[0x48];
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unsigned int req_info_permission_0; /* 0x48 */
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unsigned char res2[0x4];
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unsigned int read_permission_0; /* 0x50 */
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unsigned char res3[0x4];
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unsigned int wirte_permission_0; /* 0x58 */
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unsigned char res4[0x4];
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unsigned int addr_match_1; /* 0x58 */
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unsigned char res5[0x4];
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unsigned int req_info_permission_1; /* 0x68 */
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unsigned char res6[0x14];
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unsigned int addr_match_2; /* 0x80 */
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} pm_t;
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#endif /*__ASSEMBLY__ */
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/* Permission values for registers -Full fledged permissions to all */
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#define UNLOCK_1 0xFFFFFFFF
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#define UNLOCK_2 0x00000000
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#define UNLOCK_3 0x0000FFFF
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#define NOT_EARLY 0
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/* I2C base */
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#define I2C_BASE1 (OMAP34XX_CORE_L4_IO_BASE + 0x70000)
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#define I2C_BASE2 (OMAP34XX_CORE_L4_IO_BASE + 0x72000)
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#define I2C_BASE3 (OMAP34XX_CORE_L4_IO_BASE + 0x60000)
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#endif /* _CPU_H */
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