mirror of
https://github.com/AsahiLinux/u-boot
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321 lines
7.4 KiB
C
321 lines
7.4 KiB
C
/*
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* Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
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*
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* Driver for SPI controller on DaVinci. Based on atmel_spi.c
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* by Atmel Corporation
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*
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* Copyright (C) 2007 Atmel Corporation
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <spi.h>
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#include <malloc.h>
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#include <asm/io.h>
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#include <asm/arch/hardware.h>
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#include "davinci_spi.h"
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void spi_init()
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{
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/* do nothing */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct davinci_spi_slave *ds;
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if (!spi_cs_is_valid(bus, cs))
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return NULL;
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ds = spi_alloc_slave(struct davinci_spi_slave, bus, cs);
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if (!ds)
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return NULL;
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ds->slave.bus = bus;
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ds->slave.cs = cs;
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switch (bus) {
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case SPI0_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI0_BASE;
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break;
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#ifdef CONFIG_SYS_SPI1
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case SPI1_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI1_BASE;
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break;
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#endif
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#ifdef CONFIG_SYS_SPI2
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case SPI2_BUS:
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ds->regs = (struct davinci_spi_regs *)SPI2_BASE;
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break;
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#endif
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default: /* Invalid bus number */
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return NULL;
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}
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ds->freq = max_hz;
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return &ds->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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free(ds);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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unsigned int scalar;
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/* Enable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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udelay(1000);
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writel(SPIGCR0_SPIENA_MASK, &ds->regs->gcr0);
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/* Set master mode, powered up and not activated */
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writel(SPIGCR1_MASTER_MASK | SPIGCR1_CLKMOD_MASK, &ds->regs->gcr1);
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/* CS, CLK, SIMO and SOMI are functional pins */
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writel(((1 << slave->cs) | SPIPC0_CLKFUN_MASK |
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SPIPC0_DOFUN_MASK | SPIPC0_DIFUN_MASK), &ds->regs->pc0);
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/* setup format */
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scalar = ((CONFIG_SYS_SPI_CLK / ds->freq) - 1) & 0xFF;
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/*
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* Use following format:
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* character length = 8,
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* clock signal delayed by half clk cycle,
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* clock low in idle state - Mode 0,
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* MSB shifted out first
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*/
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writel(8 | (scalar << SPIFMT_PRESCALE_SHIFT) |
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(1 << SPIFMT_PHASE_SHIFT), &ds->regs->fmt0);
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/*
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* Including a minor delay. No science here. Should be good even with
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* no delay
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*/
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writel((50 << SPI_C2TDELAY_SHIFT) |
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(50 << SPI_T2CDELAY_SHIFT), &ds->regs->delay);
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/* default chip select register */
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writel(SPIDEF_CSDEF0_MASK, &ds->regs->def);
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/* no interrupts */
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writel(0, &ds->regs->int0);
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writel(0, &ds->regs->lvl);
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/* enable SPI */
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writel((readl(&ds->regs->gcr1) | SPIGCR1_SPIENA_MASK), &ds->regs->gcr1);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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/* Disable the SPI hardware */
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writel(SPIGCR0_SPIRST_MASK, &ds->regs->gcr0);
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}
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/*
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* This functions needs to act like a macro to avoid pipeline reloads in the
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* loops below. Use always_inline. This gains us about 160KiB/s and the bloat
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* appears to be zero bytes (da830).
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*/
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__attribute__((always_inline))
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static inline u32 davinci_spi_xfer_data(struct davinci_spi_slave *ds, u32 data)
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{
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u32 buf_reg_val;
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/* send out data */
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writel(data, &ds->regs->dat1);
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/* wait for the data to clock in/out */
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while ((buf_reg_val = readl(&ds->regs->buf)) & SPIBUF_RXEMPTY_MASK)
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;
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return buf_reg_val;
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}
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static int davinci_spi_read(struct spi_slave *slave, unsigned int len,
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u8 *rxp, unsigned long flags)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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unsigned int data1_reg_val;
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/* enable CS hold, CS[n] and clear the data bits */
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data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
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(slave->cs << SPIDAT1_CSNR_SHIFT));
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/* wait till TXFULL is deasserted */
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while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
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;
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/* preload the TX buffer to avoid clock starvation */
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writel(data1_reg_val, &ds->regs->dat1);
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/* keep reading 1 byte until only 1 byte left */
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while ((len--) > 1)
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*rxp++ = davinci_spi_xfer_data(ds, data1_reg_val);
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/* clear CS hold when we reach the end */
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if (flags & SPI_XFER_END)
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data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
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/* read the last byte */
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*rxp = davinci_spi_xfer_data(ds, data1_reg_val);
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return 0;
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}
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static int davinci_spi_write(struct spi_slave *slave, unsigned int len,
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const u8 *txp, unsigned long flags)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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unsigned int data1_reg_val;
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/* enable CS hold and clear the data bits */
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data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
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(slave->cs << SPIDAT1_CSNR_SHIFT));
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/* wait till TXFULL is deasserted */
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while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
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;
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/* preload the TX buffer to avoid clock starvation */
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if (len > 2) {
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writel(data1_reg_val | *txp++, &ds->regs->dat1);
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len--;
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}
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/* keep writing 1 byte until only 1 byte left */
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while ((len--) > 1)
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davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
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/* clear CS hold when we reach the end */
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if (flags & SPI_XFER_END)
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data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
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/* write the last byte */
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davinci_spi_xfer_data(ds, data1_reg_val | *txp);
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return 0;
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}
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#ifndef CONFIG_SPI_HALF_DUPLEX
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static int davinci_spi_read_write(struct spi_slave *slave, unsigned int len,
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u8 *rxp, const u8 *txp, unsigned long flags)
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{
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struct davinci_spi_slave *ds = to_davinci_spi(slave);
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unsigned int data1_reg_val;
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/* enable CS hold and clear the data bits */
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data1_reg_val = ((1 << SPIDAT1_CSHOLD_SHIFT) |
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(slave->cs << SPIDAT1_CSNR_SHIFT));
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/* wait till TXFULL is deasserted */
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while (readl(&ds->regs->buf) & SPIBUF_TXFULL_MASK)
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;
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/* keep reading and writing 1 byte until only 1 byte left */
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while ((len--) > 1)
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*rxp++ = davinci_spi_xfer_data(ds, data1_reg_val | *txp++);
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/* clear CS hold when we reach the end */
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if (flags & SPI_XFER_END)
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data1_reg_val &= ~(1 << SPIDAT1_CSHOLD_SHIFT);
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/* read and write the last byte */
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*rxp = davinci_spi_xfer_data(ds, data1_reg_val | *txp);
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return 0;
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}
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#endif
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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unsigned int len;
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if (bitlen == 0)
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/* Finish any previously submitted transfers */
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goto out;
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/*
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* It's not clear how non-8-bit-aligned transfers are supposed to be
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* represented as a stream of bytes...this is a limitation of
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* the current SPI interface - here we terminate on receiving such a
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* transfer request.
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*/
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if (bitlen % 8) {
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/* Errors always terminate an ongoing transfer */
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flags |= SPI_XFER_END;
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goto out;
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}
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len = bitlen / 8;
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if (!dout)
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return davinci_spi_read(slave, len, din, flags);
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else if (!din)
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return davinci_spi_write(slave, len, dout, flags);
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#ifndef CONFIG_SPI_HALF_DUPLEX
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else
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return davinci_spi_read_write(slave, len, din, dout, flags);
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#else
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printf("SPI full duplex transaction requested with "
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"CONFIG_SPI_HALF_DUPLEX defined.\n");
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flags |= SPI_XFER_END;
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#endif
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out:
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if (flags & SPI_XFER_END) {
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u8 dummy = 0;
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davinci_spi_write(slave, 1, &dummy, flags);
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}
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return 0;
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}
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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{
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int ret = 0;
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switch (bus) {
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case SPI0_BUS:
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if (cs < SPI0_NUM_CS)
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ret = 1;
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break;
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#ifdef CONFIG_SYS_SPI1
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case SPI1_BUS:
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if (cs < SPI1_NUM_CS)
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ret = 1;
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break;
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#endif
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#ifdef CONFIG_SYS_SPI2
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case SPI2_BUS:
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if (cs < SPI2_NUM_CS)
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ret = 1;
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break;
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#endif
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default:
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/* Invalid bus number. Do nothing */
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break;
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}
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return ret;
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}
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void spi_cs_activate(struct spi_slave *slave)
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{
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/* do nothing */
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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/* do nothing */
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}
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