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678398b19e
In preparation for the SoCFPGA support of the designware I2C driver, convert this driver to the common CONFIG_SYS_I2C framework. This patch converts all users of this driver, this is: - ST spearxxx boards - AXS101 (ARC700 platform) I couldn't test this patch on those boards. Only compile tested for all spear boards. And tested on SoCFPGA. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Acked-by: Alexey Brodkin <abrodkin@synopsys.com> Tested-by: Alexey Brodkin <abrodkin@synopsys.com> Cc: Heiko Schocher <hs@denx.de> Cc: Vipin Kumar <vk.vipin@gmail.com> Cc: Jeroen Hofstee <jeroen@myspectrum.nl>
402 lines
9.6 KiB
C
402 lines
9.6 KiB
C
/*
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* (C) Copyright 2009
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* Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <i2c.h>
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#include <asm/io.h>
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#include "designware_i2c.h"
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static struct i2c_regs *i2c_get_base(struct i2c_adapter *adap)
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{
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switch (adap->hwadapnr) {
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#if CONFIG_SYS_I2C_BUS_MAX >= 4
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case 3:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE3;
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 3
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case 2:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE2;
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 2
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case 1:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE1;
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#endif
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case 0:
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return (struct i2c_regs *)CONFIG_SYS_I2C_BASE;
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default:
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printf("Wrong I2C-adapter number %d\n", adap->hwadapnr);
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}
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return NULL;
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}
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/*
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* set_speed - Set the i2c speed mode (standard, high, fast)
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* @i2c_spd: required i2c speed mode
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*
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* Set the i2c speed mode (standard, high, fast)
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*/
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static void set_speed(struct i2c_adapter *adap, int i2c_spd)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned int cntl;
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unsigned int hcnt, lcnt;
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unsigned int enbl;
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/* to set speed cltr must be disabled */
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enbl = readl(&i2c_base->ic_enable);
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enbl &= ~IC_ENABLE_0B;
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writel(enbl, &i2c_base->ic_enable);
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cntl = (readl(&i2c_base->ic_con) & (~IC_CON_SPD_MSK));
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switch (i2c_spd) {
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case IC_SPEED_MODE_MAX:
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cntl |= IC_CON_SPD_HS;
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hcnt = (IC_CLK * MIN_HS_SCL_HIGHTIME) / NANO_TO_MICRO;
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writel(hcnt, &i2c_base->ic_hs_scl_hcnt);
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lcnt = (IC_CLK * MIN_HS_SCL_LOWTIME) / NANO_TO_MICRO;
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writel(lcnt, &i2c_base->ic_hs_scl_lcnt);
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break;
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case IC_SPEED_MODE_STANDARD:
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cntl |= IC_CON_SPD_SS;
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hcnt = (IC_CLK * MIN_SS_SCL_HIGHTIME) / NANO_TO_MICRO;
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writel(hcnt, &i2c_base->ic_ss_scl_hcnt);
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lcnt = (IC_CLK * MIN_SS_SCL_LOWTIME) / NANO_TO_MICRO;
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writel(lcnt, &i2c_base->ic_ss_scl_lcnt);
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break;
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case IC_SPEED_MODE_FAST:
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default:
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cntl |= IC_CON_SPD_FS;
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hcnt = (IC_CLK * MIN_FS_SCL_HIGHTIME) / NANO_TO_MICRO;
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writel(hcnt, &i2c_base->ic_fs_scl_hcnt);
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lcnt = (IC_CLK * MIN_FS_SCL_LOWTIME) / NANO_TO_MICRO;
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writel(lcnt, &i2c_base->ic_fs_scl_lcnt);
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break;
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}
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writel(cntl, &i2c_base->ic_con);
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/* Enable back i2c now speed set */
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enbl |= IC_ENABLE_0B;
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writel(enbl, &i2c_base->ic_enable);
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}
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/*
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* i2c_set_bus_speed - Set the i2c speed
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* @speed: required i2c speed
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*
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* Set the i2c speed.
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*/
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static unsigned int dw_i2c_set_bus_speed(struct i2c_adapter *adap,
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unsigned int speed)
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{
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int i2c_spd;
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if (speed >= I2C_MAX_SPEED)
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i2c_spd = IC_SPEED_MODE_MAX;
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else if (speed >= I2C_FAST_SPEED)
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i2c_spd = IC_SPEED_MODE_FAST;
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else
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i2c_spd = IC_SPEED_MODE_STANDARD;
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set_speed(adap, i2c_spd);
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adap->speed = speed;
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return 0;
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}
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/*
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* i2c_init - Init function
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* @speed: required i2c speed
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* @slaveaddr: slave address for the device
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*
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* Initialization function.
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*/
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static void dw_i2c_init(struct i2c_adapter *adap, int speed,
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int slaveaddr)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned int enbl;
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/* Disable i2c */
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enbl = readl(&i2c_base->ic_enable);
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enbl &= ~IC_ENABLE_0B;
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writel(enbl, &i2c_base->ic_enable);
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writel((IC_CON_SD | IC_CON_SPD_FS | IC_CON_MM), &i2c_base->ic_con);
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writel(IC_RX_TL, &i2c_base->ic_rx_tl);
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writel(IC_TX_TL, &i2c_base->ic_tx_tl);
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dw_i2c_set_bus_speed(adap, speed);
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writel(IC_STOP_DET, &i2c_base->ic_intr_mask);
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writel(slaveaddr, &i2c_base->ic_sar);
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/* Enable i2c */
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enbl = readl(&i2c_base->ic_enable);
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enbl |= IC_ENABLE_0B;
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writel(enbl, &i2c_base->ic_enable);
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}
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/*
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* i2c_setaddress - Sets the target slave address
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* @i2c_addr: target i2c address
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*
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* Sets the target slave address.
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*/
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static void i2c_setaddress(struct i2c_adapter *adap, unsigned int i2c_addr)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned int enbl;
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/* Disable i2c */
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enbl = readl(&i2c_base->ic_enable);
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enbl &= ~IC_ENABLE_0B;
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writel(enbl, &i2c_base->ic_enable);
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writel(i2c_addr, &i2c_base->ic_tar);
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/* Enable i2c */
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enbl = readl(&i2c_base->ic_enable);
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enbl |= IC_ENABLE_0B;
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writel(enbl, &i2c_base->ic_enable);
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}
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/*
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* i2c_flush_rxfifo - Flushes the i2c RX FIFO
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*
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* Flushes the i2c RX FIFO
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*/
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static void i2c_flush_rxfifo(struct i2c_adapter *adap)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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while (readl(&i2c_base->ic_status) & IC_STATUS_RFNE)
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readl(&i2c_base->ic_cmd_data);
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}
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/*
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* i2c_wait_for_bb - Waits for bus busy
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*
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* Waits for bus busy
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*/
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static int i2c_wait_for_bb(struct i2c_adapter *adap)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned long start_time_bb = get_timer(0);
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while ((readl(&i2c_base->ic_status) & IC_STATUS_MA) ||
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!(readl(&i2c_base->ic_status) & IC_STATUS_TFE)) {
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/* Evaluate timeout */
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if (get_timer(start_time_bb) > (unsigned long)(I2C_BYTE_TO_BB))
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return 1;
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}
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return 0;
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}
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static int i2c_xfer_init(struct i2c_adapter *adap, uchar chip, uint addr,
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int alen)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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if (i2c_wait_for_bb(adap))
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return 1;
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i2c_setaddress(adap, chip);
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while (alen) {
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alen--;
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/* high byte address going out first */
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writel((addr >> (alen * 8)) & 0xff,
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&i2c_base->ic_cmd_data);
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}
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return 0;
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}
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static int i2c_xfer_finish(struct i2c_adapter *adap)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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ulong start_stop_det = get_timer(0);
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while (1) {
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if ((readl(&i2c_base->ic_raw_intr_stat) & IC_STOP_DET)) {
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readl(&i2c_base->ic_clr_stop_det);
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break;
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} else if (get_timer(start_stop_det) > I2C_STOPDET_TO) {
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break;
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}
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}
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if (i2c_wait_for_bb(adap)) {
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printf("Timed out waiting for bus\n");
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return 1;
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}
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i2c_flush_rxfifo(adap);
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return 0;
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}
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/*
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* i2c_read - Read from i2c memory
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* @chip: target i2c address
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* @addr: address to read from
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* @alen:
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* @buffer: buffer for read data
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* @len: no of bytes to be read
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*
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* Read from i2c memory.
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*/
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static int dw_i2c_read(struct i2c_adapter *adap, u8 dev, uint addr,
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int alen, u8 *buffer, int len)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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unsigned long start_time_rx;
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
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debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
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addr);
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#endif
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if (i2c_xfer_init(adap, dev, addr, alen))
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return 1;
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start_time_rx = get_timer(0);
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while (len) {
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if (len == 1)
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writel(IC_CMD | IC_STOP, &i2c_base->ic_cmd_data);
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else
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writel(IC_CMD, &i2c_base->ic_cmd_data);
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if (readl(&i2c_base->ic_status) & IC_STATUS_RFNE) {
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*buffer++ = (uchar)readl(&i2c_base->ic_cmd_data);
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len--;
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start_time_rx = get_timer(0);
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} else if (get_timer(start_time_rx) > I2C_BYTE_TO) {
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return 1;
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}
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}
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return i2c_xfer_finish(adap);
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}
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/*
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* i2c_write - Write to i2c memory
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* @chip: target i2c address
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* @addr: address to read from
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* @alen:
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* @buffer: buffer for read data
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* @len: no of bytes to be read
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*
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* Write to i2c memory.
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*/
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static int dw_i2c_write(struct i2c_adapter *adap, u8 dev, uint addr,
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int alen, u8 *buffer, int len)
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{
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struct i2c_regs *i2c_base = i2c_get_base(adap);
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int nb = len;
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unsigned long start_time_tx;
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#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
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/*
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* EEPROM chips that implement "address overflow" are ones
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* like Catalyst 24WC04/08/16 which has 9/10/11 bits of
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* address and the extra bits end up in the "chip address"
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* bit slots. This makes a 24WC08 (1Kbyte) chip look like
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* four 256 byte chips.
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*
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* Note that we consider the length of the address field to
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* still be one byte because the extra address bits are
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* hidden in the chip address.
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*/
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dev |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
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addr &= ~(CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW << (alen * 8));
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debug("%s: fix addr_overflow: dev %02x addr %02x\n", __func__, dev,
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addr);
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#endif
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if (i2c_xfer_init(adap, dev, addr, alen))
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return 1;
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start_time_tx = get_timer(0);
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while (len) {
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if (readl(&i2c_base->ic_status) & IC_STATUS_TFNF) {
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if (--len == 0) {
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writel(*buffer | IC_STOP,
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&i2c_base->ic_cmd_data);
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} else {
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writel(*buffer, &i2c_base->ic_cmd_data);
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}
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buffer++;
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start_time_tx = get_timer(0);
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} else if (get_timer(start_time_tx) > (nb * I2C_BYTE_TO)) {
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printf("Timed out. i2c write Failed\n");
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return 1;
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}
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}
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return i2c_xfer_finish(adap);
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}
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/*
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* i2c_probe - Probe the i2c chip
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*/
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static int dw_i2c_probe(struct i2c_adapter *adap, u8 dev)
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{
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u32 tmp;
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int ret;
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/*
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* Try to read the first location of the chip.
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*/
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ret = dw_i2c_read(adap, dev, 0, 1, (uchar *)&tmp, 1);
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if (ret)
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dw_i2c_init(adap, adap->speed, adap->slaveaddr);
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return ret;
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}
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U_BOOT_I2C_ADAP_COMPLETE(dw_0, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
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dw_i2c_write, dw_i2c_set_bus_speed,
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CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, 0)
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#if CONFIG_SYS_I2C_BUS_MAX >= 2
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U_BOOT_I2C_ADAP_COMPLETE(dw_1, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
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dw_i2c_write, dw_i2c_set_bus_speed,
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CONFIG_SYS_I2C_SPEED1, CONFIG_SYS_I2C_SLAVE1, 1)
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 3
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U_BOOT_I2C_ADAP_COMPLETE(dw_2, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
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dw_i2c_write, dw_i2c_set_bus_speed,
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CONFIG_SYS_I2C_SPEED2, CONFIG_SYS_I2C_SLAVE2, 2)
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#endif
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#if CONFIG_SYS_I2C_BUS_MAX >= 4
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U_BOOT_I2C_ADAP_COMPLETE(dw_3, dw_i2c_init, dw_i2c_probe, dw_i2c_read,
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dw_i2c_write, dw_i2c_set_bus_speed,
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CONFIG_SYS_I2C_SPEED3, CONFIG_SYS_I2C_SLAVE3, 3)
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#endif
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