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c79cba37b3
The macro MIN, MAX is defined as the aliase of min, max, respectively. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
168 lines
3.9 KiB
C
168 lines
3.9 KiB
C
/*
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* Copyright 2004,2007,2008 Freescale Semiconductor, Inc.
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* (C) Copyright 2002, 2003 Motorola Inc.
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* Xianghua Xiao (X.Xiao@motorola.com)
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/fsl_dma.h>
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/* Controller can only transfer 2^26 - 1 bytes at a time */
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#define FSL_DMA_MAX_SIZE (0x3ffffff)
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#if defined(CONFIG_MPC83xx)
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#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_CTM_DIRECT | FSL_DMA_MR_DMSEN)
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#else
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#define FSL_DMA_MR_DEFAULT (FSL_DMA_MR_BWC_DIS | FSL_DMA_MR_CTM_DIRECT)
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#endif
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#if defined(CONFIG_MPC83xx)
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dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR);
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#elif defined(CONFIG_MPC85xx)
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ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR);
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#elif defined(CONFIG_MPC86xx)
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ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR);
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#else
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#error "Freescale DMA engine not supported on your processor"
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#endif
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static void dma_sync(void)
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{
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#if defined(CONFIG_MPC85xx)
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asm("sync; isync; msync");
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#elif defined(CONFIG_MPC86xx)
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asm("sync; isync");
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#endif
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}
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static void out_dma32(volatile unsigned *addr, int val)
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{
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#if defined(CONFIG_MPC83xx)
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out_le32(addr, val);
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#else
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out_be32(addr, val);
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#endif
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}
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static uint in_dma32(volatile unsigned *addr)
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{
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#if defined(CONFIG_MPC83xx)
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return in_le32(addr);
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#else
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return in_be32(addr);
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#endif
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}
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static uint dma_check(void) {
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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uint status;
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/* While the channel is busy, spin */
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do {
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status = in_dma32(&dma->sr);
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} while (status & FSL_DMA_SR_CB);
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/* clear MR[CS] channel start bit */
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out_dma32(&dma->mr, in_dma32(&dma->mr) & ~FSL_DMA_MR_CS);
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dma_sync();
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if (status != 0)
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printf ("DMA Error: status = %x\n", status);
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return status;
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}
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#if !defined(CONFIG_MPC83xx)
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void dma_init(void) {
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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out_dma32(&dma->satr, FSL_DMA_SATR_SREAD_SNOOP);
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out_dma32(&dma->datr, FSL_DMA_DATR_DWRITE_SNOOP);
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out_dma32(&dma->sr, 0xffffffff); /* clear any errors */
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dma_sync();
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}
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#endif
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int dmacpy(phys_addr_t dest, phys_addr_t src, phys_size_t count) {
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volatile fsl_dma_t *dma = &dma_base->dma[0];
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uint xfer_size;
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while (count) {
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xfer_size = min(FSL_DMA_MAX_SIZE, count);
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out_dma32(&dma->dar, (u32) (dest & 0xFFFFFFFF));
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out_dma32(&dma->sar, (u32) (src & 0xFFFFFFFF));
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#if !defined(CONFIG_MPC83xx)
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out_dma32(&dma->satr,
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in_dma32(&dma->satr) | (u32)((u64)src >> 32));
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out_dma32(&dma->datr,
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in_dma32(&dma->datr) | (u32)((u64)dest >> 32));
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#endif
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out_dma32(&dma->bcr, xfer_size);
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dma_sync();
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/* Prepare mode register */
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out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT);
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dma_sync();
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/* Start the transfer */
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out_dma32(&dma->mr, FSL_DMA_MR_DEFAULT | FSL_DMA_MR_CS);
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count -= xfer_size;
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src += xfer_size;
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dest += xfer_size;
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dma_sync();
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if (dma_check())
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return -1;
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}
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return 0;
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}
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/*
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* 85xx/86xx use dma to initialize SDRAM when !CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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* while 83xx uses dma to initialize SDRAM when CONFIG_DDR_ECC_INIT_VIA_DMA
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*/
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#if ((!defined CONFIG_MPC83xx && defined(CONFIG_DDR_ECC) && \
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!defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)) || \
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(defined(CONFIG_MPC83xx) && defined(CONFIG_DDR_ECC_INIT_VIA_DMA)))
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void dma_meminit(uint val, uint size)
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{
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uint *p = 0;
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uint i = 0;
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for (*p = 0; p < (uint *)(8 * 1024); p++) {
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if (((uint)p & 0x1f) == 0)
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ppcDcbz((ulong)p);
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*p = (uint)CONFIG_MEM_INIT_VALUE;
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if (((uint)p & 0x1c) == 0x1c)
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ppcDcbf((ulong)p);
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}
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dmacpy(0x002000, 0, 0x002000); /* 8K */
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dmacpy(0x004000, 0, 0x004000); /* 16K */
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dmacpy(0x008000, 0, 0x008000); /* 32K */
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dmacpy(0x010000, 0, 0x010000); /* 64K */
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dmacpy(0x020000, 0, 0x020000); /* 128K */
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dmacpy(0x040000, 0, 0x040000); /* 256K */
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dmacpy(0x080000, 0, 0x080000); /* 512K */
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dmacpy(0x100000, 0, 0x100000); /* 1M */
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dmacpy(0x200000, 0, 0x200000); /* 2M */
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dmacpy(0x400000, 0, 0x400000); /* 4M */
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for (i = 1; i < size / 0x800000; i++)
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dmacpy((0x800000 * i), 0, 0x800000);
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}
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#endif
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