mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-01 17:10:11 +00:00
174d728471
Update my and DPs email address to match current setup. Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/aba5b19b9c5a95608829e86ad5cc4671c940f1bb.1688992543.git.michal.simek@amd.com
65 lines
1.1 KiB
Text
65 lines
1.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* dts file for Xilinx Versal Mini eMMC1 Configuration
|
|
*
|
|
* (C) Copyright 2018-2019, Xilinx, Inc.
|
|
*
|
|
* Siva Durga Prasad <siva.durga.prasad.paladugu@amd.com>>
|
|
* Michal Simek <michal.simek@amd.com>
|
|
*/
|
|
|
|
/dts-v1/;
|
|
|
|
/ {
|
|
compatible = "xlnx,versal";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
model = "Xilinx Versal MINI eMMC1";
|
|
|
|
clk200: clk200 {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0x0>;
|
|
clock-frequency = <200000000>;
|
|
};
|
|
|
|
dcc: dcc {
|
|
compatible = "arm,dcc";
|
|
status = "okay";
|
|
bootph-all;
|
|
};
|
|
|
|
amba: amba {
|
|
bootph-all;
|
|
compatible = "simple-bus";
|
|
#address-cells = <0x2>;
|
|
#size-cells = <0x2>;
|
|
ranges;
|
|
|
|
sdhci1: sdhci@f1050000 {
|
|
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
|
|
status = "okay";
|
|
non-removable;
|
|
disable-wp;
|
|
bus-width = <8>;
|
|
reg = <0x0 0xf1050000 0x0 0x10000>;
|
|
clock-names = "clk_xin", "clk_ahb";
|
|
clocks = <&clk200 &clk200>;
|
|
no-1-8-v;
|
|
xlnx,mio-bank = <0>;
|
|
};
|
|
};
|
|
|
|
aliases {
|
|
serial0 = &dcc;
|
|
mmc0 = &sdhci1;
|
|
};
|
|
|
|
chosen {
|
|
stdout-path = "serial0:115200";
|
|
};
|
|
|
|
memory@0 {
|
|
device_type = "memory";
|
|
reg = <0x0 0x0 0x0 0x20000000>;
|
|
};
|
|
};
|