mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-11 07:34:31 +00:00
c837dcb1a3
before we can access it; add delay in case we are faster (with no CF card inserted) * Cleanup of some init functions * Make sure SCC Ethernet is always stopped by the time we boot Linux to avoid Linux crashes by early packets coming in. * Accelerate flash accesses on LWMON board by using buffered writes
155 lines
5.5 KiB
C
155 lines
5.5 KiB
C
#ifndef __LINUX_PS2MULT_H
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#define __LINUX_PS2MULT_H
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#define kbd_request_region() ps2mult_init()
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#define kbd_request_irq(handler) ps2mult_request_irq(handler)
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#define kbd_read_input() ps2mult_read_input()
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#define kbd_read_status() ps2mult_read_status()
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#define kbd_write_output(val) ps2mult_write_output(val)
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#define kbd_write_command(val) ps2mult_write_command(val)
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#define aux_request_irq(hand, dev_id) 0
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#define aux_free_irq(dev_id)
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#define PS2MULT_KB_SELECTOR 0xA0
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#define PS2MULT_MS_SELECTOR 0xA1
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#define PS2MULT_ESCAPE 0x7D
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#define PS2MULT_BSYNC 0x7E
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#define PS2MULT_SESSION_START 0x55
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#define PS2MULT_SESSION_END 0x56
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#define PS2BUF_SIZE 512 /* power of 2, please */
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#ifndef CONFIG_PS2MULT_DELAY
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#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
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#endif
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/* PS/2 controller interface (include/asm/keyboard.h)
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*/
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extern int ps2mult_init (void);
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extern int ps2mult_request_irq(void (*handler)(void *));
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extern u_char ps2mult_read_input(void);
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extern u_char ps2mult_read_status(void);
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extern void ps2mult_write_output(u_char val);
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extern void ps2mult_write_command(u_char val);
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extern void ps2mult_early_init (void);
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extern void ps2mult_callback (int in_cnt);
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/* Simple serial interface
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*/
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extern int ps2ser_init(void);
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extern void ps2ser_putc(int chr);
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extern int ps2ser_getc(void);
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extern int ps2ser_check(void);
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/* Serial related stuff
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*/
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struct serial_state {
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int baud_base;
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int irq;
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u8 *iomem_base;
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};
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#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
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#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
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#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
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#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
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#define UART_IER 1 /* Out: Interrupt Enable Register */
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#define UART_IIR 2 /* In: Interrupt ID Register */
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#define UART_FCR 2 /* Out: FIFO Control Register */
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#define UART_LCR 3 /* Out: Line Control Register */
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#define UART_MCR 4 /* Out: Modem Control Register */
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#define UART_LSR 5 /* In: Line Status Register */
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#define UART_MSR 6 /* In: Modem Status Register */
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#define UART_SCR 7 /* I/O: Scratch Register */
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/*
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* These are the definitions for the FIFO Control Register
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* (16650 only)
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*/
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#define UART_FCR_ENABLE_FIFO 0x01 /* Enable the FIFO */
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#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
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#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
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#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
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#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
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#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
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#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
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#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
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/*
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* These are the definitions for the Line Control Register
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*
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* Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
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* UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
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*/
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_LCR_SBC 0x40 /* Set break control */
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#define UART_LCR_SPAR 0x20 /* Stick parity (?) */
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#define UART_LCR_EPAR 0x10 /* Even parity select */
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#define UART_LCR_PARITY 0x08 /* Parity Enable */
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#define UART_LCR_STOP 0x04 /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
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#define UART_LCR_WLEN5 0x00 /* Wordlength: 5 bits */
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#define UART_LCR_WLEN6 0x01 /* Wordlength: 6 bits */
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#define UART_LCR_WLEN7 0x02 /* Wordlength: 7 bits */
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#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
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/*
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* These are the definitions for the Line Status Register
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*/
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#define UART_LSR_TEMT 0x40 /* Transmitter empty */
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#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
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#define UART_LSR_BI 0x10 /* Break interrupt indicator */
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#define UART_LSR_FE 0x08 /* Frame error indicator */
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#define UART_LSR_PE 0x04 /* Parity error indicator */
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#define UART_LSR_OE 0x02 /* Overrun error indicator */
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#define UART_LSR_DR 0x01 /* Receiver data ready */
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/*
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* These are the definitions for the Interrupt Identification Register
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*/
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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/*
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* These are the definitions for the Interrupt Enable Register
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*/
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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/*
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* These are the definitions for the Modem Control Register
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*/
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_MCR_OUT2 0x08 /* Out2 complement */
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#define UART_MCR_OUT1 0x04 /* Out1 complement */
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#define UART_MCR_RTS 0x02 /* RTS complement */
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#define UART_MCR_DTR 0x01 /* DTR complement */
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/*
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* These are the definitions for the Modem Status Register
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*/
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
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#endif /* __LINUX_PS2MULT_H */
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