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3cc7942a4a
RAM repair has a few pre-requisites: 1) PMIC power supply (rail) enabled. 2) PMC CRAIL power partition powered. 3) Fuse clock active (it's the default). 4) PLLP reshift branch enabled (it's the default, when PLLP is active). RAM repair also only need run whenever specific partitions are powered (main SoC and CCPLEX respectively); RAM repair does not need to be triggered when any other partition changes state. start_cpu() needs to be re-ordered slightly to match these requirements. Note that C0NC and CE0 aren't required for RAM repair to operate, but they also do no harm, so the entire of powerup_cpus() is moved rather than splitting it up. The call to remove_cpu_resets() is moved last to ensure that all other actions complete before releasing reset; since the PMC power partitions are now enabled early, releasing reset is what causes the CPUs to start executing code, and RAM repair must complete before the CPU boots. Note that this commit is the result of squashing a numbmer of commits in NVIDIA's downstream L4T branch, hence the multiple signoffs below. Signed-off-by: Bibek Basu <bbasu@nvidia.com> Signed-off-by: Sandipan Patra <spatra@nvidia.com> Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com> |
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| .. | ||
| ahb.h | ||
| clock-tables.h | ||
| clock.h | ||
| display.h | ||
| flow.h | ||
| funcmux.h | ||
| gp_padctrl.h | ||
| gpio.h | ||
| mc.h | ||
| pinmux.h | ||
| pmu.h | ||
| powergate.h | ||
| pwm.h | ||
| sysctr.h | ||
| tegra.h | ||