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https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
234 lines
4.9 KiB
C
234 lines
4.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2015 Google, Inc
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*
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* (C) Copyright 2008-2014 Rockchip Electronics
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* Peter, Software Engineering, <superpeter.cai@gmail.com>.
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*/
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#ifndef _ASM_ARCH_CRU_RK3288_H
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#define _ASM_ARCH_CRU_RK3288_H
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#define OSC_HZ (24 * 1000 * 1000)
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#define APLL_HZ (1800 * 1000000)
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#define GPLL_HZ (594 * 1000000)
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#define CPLL_HZ (384 * 1000000)
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#define NPLL_HZ (384 * 1000000)
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/* The SRAM is clocked off aclk_bus, so we want to max it out for boot speed */
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#define PD_BUS_ACLK_HZ 297000000
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#define PD_BUS_HCLK_HZ 148500000
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#define PD_BUS_PCLK_HZ 74250000
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#define PERI_ACLK_HZ 148500000
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#define PERI_HCLK_HZ 148500000
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#define PERI_PCLK_HZ 74250000
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/* Private data for the clock driver - used by rockchip_get_cru() */
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struct rk3288_clk_priv {
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struct rk3288_grf *grf;
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struct rk3288_cru *cru;
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ulong rate;
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};
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struct rk3288_cru {
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struct rk3288_pll {
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u32 con0;
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u32 con1;
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u32 con2;
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u32 con3;
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} pll[5];
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u32 cru_mode_con;
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u32 reserved0[3];
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u32 cru_clksel_con[43];
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u32 reserved1[21];
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u32 cru_clkgate_con[19];
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u32 reserved2;
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u32 cru_glb_srst_fst_value;
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u32 cru_glb_srst_snd_value;
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u32 cru_softrst_con[12];
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u32 cru_misc_con;
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u32 cru_glb_cnt_th;
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u32 cru_glb_rst_con;
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u32 reserved3;
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u32 cru_glb_rst_st;
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u32 reserved4;
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u32 cru_sdmmc_con[2];
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u32 cru_sdio0_con[2];
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u32 cru_sdio1_con[2];
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u32 cru_emmc_con[2];
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};
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check_member(rk3288_cru, cru_emmc_con[1], 0x021c);
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/* CRU_CLKSEL11_CON */
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enum {
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HSICPHY_DIV_SHIFT = 8,
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HSICPHY_DIV_MASK = 0x3f << HSICPHY_DIV_SHIFT,
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MMC0_PLL_SHIFT = 6,
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MMC0_PLL_MASK = 3 << MMC0_PLL_SHIFT,
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MMC0_PLL_SELECT_CODEC = 0,
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MMC0_PLL_SELECT_GENERAL,
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MMC0_PLL_SELECT_24MHZ,
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MMC0_DIV_SHIFT = 0,
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MMC0_DIV_MASK = 0x3f << MMC0_DIV_SHIFT,
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};
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/* CRU_CLKSEL12_CON */
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enum {
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EMMC_PLL_SHIFT = 0xe,
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EMMC_PLL_MASK = 3 << EMMC_PLL_SHIFT,
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EMMC_PLL_SELECT_CODEC = 0,
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EMMC_PLL_SELECT_GENERAL,
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EMMC_PLL_SELECT_24MHZ,
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EMMC_DIV_SHIFT = 8,
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EMMC_DIV_MASK = 0x3f << EMMC_DIV_SHIFT,
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SDIO0_PLL_SHIFT = 6,
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SDIO0_PLL_MASK = 3 << SDIO0_PLL_SHIFT,
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SDIO0_PLL_SELECT_CODEC = 0,
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SDIO0_PLL_SELECT_GENERAL,
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SDIO0_PLL_SELECT_24MHZ,
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SDIO0_DIV_SHIFT = 0,
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SDIO0_DIV_MASK = 0x3f << SDIO0_DIV_SHIFT,
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};
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/* CRU_CLKSEL21_CON */
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enum {
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MAC_DIV_CON_SHIFT = 0xf,
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MAC_DIV_CON_MASK = 0x1f << MAC_DIV_CON_SHIFT,
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RMII_EXTCLK_SHIFT = 4,
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RMII_EXTCLK_MASK = 1 << RMII_EXTCLK_SHIFT,
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RMII_EXTCLK_SELECT_INT_DIV_CLK = 0,
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RMII_EXTCLK_SELECT_EXT_CLK = 1,
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EMAC_PLL_SHIFT = 0,
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EMAC_PLL_MASK = 0x3 << EMAC_PLL_SHIFT,
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EMAC_PLL_SELECT_NEW = 0x0,
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EMAC_PLL_SELECT_CODEC = 0x1,
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EMAC_PLL_SELECT_GENERAL = 0x2,
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};
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/* CRU_CLKSEL25_CON */
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enum {
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SPI1_PLL_SHIFT = 0xf,
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SPI1_PLL_MASK = 1 << SPI1_PLL_SHIFT,
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SPI1_PLL_SELECT_CODEC = 0,
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SPI1_PLL_SELECT_GENERAL,
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SPI1_DIV_SHIFT = 8,
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SPI1_DIV_MASK = 0x7f << SPI1_DIV_SHIFT,
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SPI0_PLL_SHIFT = 7,
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SPI0_PLL_MASK = 1 << SPI0_PLL_SHIFT,
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SPI0_PLL_SELECT_CODEC = 0,
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SPI0_PLL_SELECT_GENERAL,
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SPI0_DIV_SHIFT = 0,
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SPI0_DIV_MASK = 0x7f << SPI0_DIV_SHIFT,
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};
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/* CRU_CLKSEL37_CON */
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enum {
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PCLK_CORE_DBG_DIV_SHIFT = 9,
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PCLK_CORE_DBG_DIV_MASK = 0x1f << PCLK_CORE_DBG_DIV_SHIFT,
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ATCLK_CORE_DIV_CON_SHIFT = 4,
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ATCLK_CORE_DIV_CON_MASK = 0x1f << ATCLK_CORE_DIV_CON_SHIFT,
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CLK_L2RAM_DIV_SHIFT = 0,
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CLK_L2RAM_DIV_MASK = 7 << CLK_L2RAM_DIV_SHIFT,
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};
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/* CRU_CLKSEL39_CON */
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enum {
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ACLK_HEVC_PLL_SHIFT = 0xe,
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ACLK_HEVC_PLL_MASK = 3 << ACLK_HEVC_PLL_SHIFT,
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ACLK_HEVC_PLL_SELECT_CODEC = 0,
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ACLK_HEVC_PLL_SELECT_GENERAL,
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ACLK_HEVC_PLL_SELECT_NEW,
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ACLK_HEVC_DIV_SHIFT = 8,
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ACLK_HEVC_DIV_MASK = 0x1f << ACLK_HEVC_DIV_SHIFT,
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SPI2_PLL_SHIFT = 7,
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SPI2_PLL_MASK = 1 << SPI2_PLL_SHIFT,
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SPI2_PLL_SELECT_CODEC = 0,
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SPI2_PLL_SELECT_GENERAL,
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SPI2_DIV_SHIFT = 0,
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SPI2_DIV_MASK = 0x7f << SPI2_DIV_SHIFT,
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};
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/* CRU_MODE_CON */
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enum {
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CRU_MODE_MASK = 3,
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NPLL_MODE_SHIFT = 0xe,
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NPLL_MODE_MASK = CRU_MODE_MASK << NPLL_MODE_SHIFT,
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NPLL_MODE_SLOW = 0,
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NPLL_MODE_NORMAL,
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NPLL_MODE_DEEP,
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GPLL_MODE_SHIFT = 0xc,
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GPLL_MODE_MASK = CRU_MODE_MASK << GPLL_MODE_SHIFT,
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GPLL_MODE_SLOW = 0,
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GPLL_MODE_NORMAL,
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GPLL_MODE_DEEP,
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CPLL_MODE_SHIFT = 8,
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CPLL_MODE_MASK = CRU_MODE_MASK << CPLL_MODE_SHIFT,
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CPLL_MODE_SLOW = 0,
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CPLL_MODE_NORMAL,
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CPLL_MODE_DEEP,
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DPLL_MODE_SHIFT = 4,
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DPLL_MODE_MASK = CRU_MODE_MASK << DPLL_MODE_SHIFT,
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DPLL_MODE_SLOW = 0,
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DPLL_MODE_NORMAL,
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DPLL_MODE_DEEP,
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APLL_MODE_SHIFT = 0,
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APLL_MODE_MASK = CRU_MODE_MASK << APLL_MODE_SHIFT,
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APLL_MODE_SLOW = 0,
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APLL_MODE_NORMAL,
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APLL_MODE_DEEP,
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};
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/* CRU_APLL_CON0 */
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enum {
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CLKR_SHIFT = 8,
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CLKR_MASK = 0x3f << CLKR_SHIFT,
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CLKOD_SHIFT = 0,
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CLKOD_MASK = 0xf << CLKOD_SHIFT,
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};
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/* CRU_APLL_CON1 */
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enum {
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LOCK_SHIFT = 0x1f,
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LOCK_MASK = 1 << LOCK_SHIFT,
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LOCK_UNLOCK = 0,
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LOCK_LOCK,
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CLKF_SHIFT = 0,
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CLKF_MASK = 0x1fff << CLKF_SHIFT,
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};
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/* CRU_GLB_RST_ST */
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enum {
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GLB_POR_RST,
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FST_GLB_RST_ST = BIT(0),
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SND_GLB_RST_ST = BIT(1),
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FST_GLB_TSADC_RST_ST = BIT(2),
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SND_GLB_TSADC_RST_ST = BIT(3),
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FST_GLB_WDT_RST_ST = BIT(4),
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SND_GLB_WDT_RST_ST = BIT(5),
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GLB_RST_ST_MASK = GENMASK(5, 0),
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};
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#endif
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