mirror of
https://github.com/AsahiLinux/u-boot
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70a09c6c3d
Add support for CAR so that we have memory to use prior to DRAM init. On link there is a total of 128KB of CAR available, although some is used for the memory reference code. Signed-off-by: Simon Glass <sjg@chromium.org>
121 lines
4.2 KiB
C
121 lines
4.2 KiB
C
/*
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* Copyright (c) 2014 Google, Inc
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*
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* From Coreboot file of the same name
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _ASM_MTRR_H
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#define _ASM_MTRR_H
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/* These are the region types */
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#define MTRR_TYPE_UNCACHEABLE 0
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#define MTRR_TYPE_WRCOMB 1
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/*#define MTRR_TYPE_ 2*/
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/*#define MTRR_TYPE_ 3*/
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#define MTRR_TYPE_WRTHROUGH 4
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#define MTRR_TYPE_WRPROT 5
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#define MTRR_TYPE_WRBACK 6
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#define MTRR_NUM_TYPES 7
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#define MTRRcap_MSR 0x0fe
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#define MTRRdefType_MSR 0x2ff
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#define MTRRdefTypeEn (1 << 11)
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#define MTRRdefTypeFixEn (1 << 10)
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#define SMRRphysBase_MSR 0x1f2
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#define SMRRphysMask_MSR 0x1f3
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#define MTRRphysBase_MSR(reg) (0x200 + 2 * (reg))
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#define MTRRphysMask_MSR(reg) (0x200 + 2 * (reg) + 1)
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#define MTRRphysMaskValid (1 << 11)
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#define NUM_FIXED_RANGES 88
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#define RANGES_PER_FIXED_MTRR 8
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#define MTRRfix64K_00000_MSR 0x250
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#define MTRRfix16K_80000_MSR 0x258
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#define MTRRfix16K_A0000_MSR 0x259
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#define MTRRfix4K_C0000_MSR 0x268
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#define MTRRfix4K_C8000_MSR 0x269
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#define MTRRfix4K_D0000_MSR 0x26a
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#define MTRRfix4K_D8000_MSR 0x26b
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#define MTRRfix4K_E0000_MSR 0x26c
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#define MTRRfix4K_E8000_MSR 0x26d
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#define MTRRfix4K_F0000_MSR 0x26e
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#define MTRRfix4K_F8000_MSR 0x26f
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#if !defined(__ASSEMBLER__)
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/*
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* The MTRR code has some side effects that the callers should be aware for.
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* 1. The call sequence matters. x86_setup_mtrrs() calls
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* x86_setup_fixed_mtrrs_no_enable() then enable_fixed_mtrrs() (equivalent
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* of x86_setup_fixed_mtrrs()) then x86_setup_var_mtrrs(). If the callers
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* want to call the components of x86_setup_mtrrs() because of other
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* rquirements the ordering should still preserved.
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* 2. enable_fixed_mtrr() will enable both variable and fixed MTRRs because
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* of the nature of the global MTRR enable flag. Therefore, all direct
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* or indirect callers of enable_fixed_mtrr() should ensure that the
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* variable MTRR MSRs do not contain bad ranges.
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* 3. If CONFIG_CACHE_ROM is selected an MTRR is allocated for enabling
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* the caching of the ROM. However, it is set to uncacheable (UC). It
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* is the responsiblity of the caller to enable it by calling
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* x86_mtrr_enable_rom_caching().
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*/
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void x86_setup_mtrrs(void);
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/*
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* x86_setup_var_mtrrs() parameters:
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* address_bits - number of physical address bits supported by cpu
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* above4gb - 2 means dynamically detect number of variable MTRRs available.
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* non-zero means handle memory ranges above 4GiB.
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* 0 means ignore memory ranges above 4GiB
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*/
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void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb);
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void enable_fixed_mtrr(void);
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void x86_setup_fixed_mtrrs(void);
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/* Set up fixed MTRRs but do not enable them. */
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void x86_setup_fixed_mtrrs_no_enable(void);
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int x86_mtrr_check(void);
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/* ROM caching can be used after variable MTRRs are set up. Beware that
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* enabling CONFIG_CACHE_ROM will eat through quite a few MTRRs based on
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* one's IO hole size and WRCOMB resources. Be sure to check the console
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* log when enabling CONFIG_CACHE_ROM or adding WRCOMB resources. Beware that
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* on CPUs with core-scoped MTRR registers such as hyperthreaded CPUs the
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* rom caching will be disabled if all threads run the MTRR code. Therefore,
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* one needs to call x86_mtrr_enable_rom_caching() after all threads of the
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* same core have run the MTRR code. */
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#if CONFIG_CACHE_ROM
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void x86_mtrr_enable_rom_caching(void);
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void x86_mtrr_disable_rom_caching(void);
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/* Return the variable range MTRR index of the ROM cache. */
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long x86_mtrr_rom_cache_var_index(void);
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#else
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static inline void x86_mtrr_enable_rom_caching(void) {}
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static inline void x86_mtrr_disable_rom_caching(void) {}
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static inline long x86_mtrr_rom_cache_var_index(void) { return -1; }
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#endif /* CONFIG_CACHE_ROM */
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#endif
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#if !defined(CONFIG_RAMTOP)
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# error "CONFIG_RAMTOP not defined"
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#endif
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#if ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE - 1)) != 0)
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# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
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#endif
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#if ((CONFIG_CACHE_ROM_SIZE & (CONFIG_CACHE_ROM_SIZE - 1)) != 0)
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# error "CONFIG_CACHE_ROM_SIZE is not a power of 2"
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#endif
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#define CACHE_ROM_BASE (((1 << 20) - (CONFIG_CACHE_ROM_SIZE >> 12)) << 12)
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#if (CONFIG_RAMTOP & (CONFIG_RAMTOP - 1)) != 0
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# error "CONFIG_RAMTOP must be a power of 2"
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#endif
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#endif
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