u-boot/arch/riscv/cpu/fu540
Bin Meng a6d7e8c914 riscv: Split SiFive CLINT support between SPL and U-Boot proper
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.

This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.

To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
2021-05-17 16:42:24 +08:00
..
cache.c common: Drop asm/global_data.h from common header 2021-02-02 15:33:42 -05:00
cpu.c riscv: cpu: fu540: Add support for cpu fu540 2020-06-04 09:44:09 +08:00
dram.c Merge branch '2021-02-02-drop-asm_global_data-when-unused' 2021-02-15 10:16:45 -05:00
Kconfig riscv: Split SiFive CLINT support between SPL and U-Boot proper 2021-05-17 16:42:24 +08:00
Makefile riscv: sifive: fu540: enable all cache ways from U-Boot proper 2020-07-03 15:09:06 +08:00
spl.c Revert "riscv: cpu: fu740: clear feature disable CSR" 2021-05-14 16:26:20 +08:00