mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-14 08:57:58 +00:00
f39748ae8e
- Add support for the Logic Zoom LH7A40x based SDK board(s),
specifically the LPD7A400.
* Patches by Robert Schwebel, 15 May 2004:
- call MAC address reading code also for SMSC91C111;
- make SMSC91C111 timeout configurable, remove duplicate code
- fix get_timer() for PXA
- update doc/README.JFFS2
- use "bootfile" env variable also for jffs2
195 lines
7.2 KiB
C
195 lines
7.2 KiB
C
/*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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/*
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* Logic lh7a400-10 Card Engine CPLD interface
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*/
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#ifndef __LPD7A400_CPLD_H_
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#define __LPD7A400_CPLD_H_
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/*
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* IO Controller Address and Register Definitions
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* - using LH7A400-10 Card Engine IO Controller Specification
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* (logic PN: 70000079)
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*/
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/*------------------------------------------------------------------
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* Slow Peripherals (nCS6)
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*/
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#define LPD7A400_CPLD_CF (0x60200000)
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#define LPD7A400_CPLD_ISA (0x60400000)
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/*------------------------------------------------------------------
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* Fast Peripherals (nCS7)
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*
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* The CPLD directs access to 0x70000000-0x701fffff to the onboard
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* ethernet controller
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*/
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#define LPD7A400_CPLD_WLAN_BASE (0x70000000)
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/* All registers are 8 bit */
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#define LPD7A400_CPLD_CECTL_REG (0x70200000)
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#define LPD7A400_CPLD_SPIDATA_REG (0x70600000)
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#define LPD7A400_CPLD_SPICTL_REG (0x70800000)
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#define LPD7A400_CPLD_EEPSPI_REG (0x70a00000)
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#define LPD7A400_CPLD_INTMASK_REG (0x70c00000)
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#define LPD7A400_CPLD_MODE_REG (0x70e00000)
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#define LPD7A400_CPLD_FLASH_REG (0x71000000)
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#define LPD7A400_CPLD_PWRMG_REG (0x71200000)
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#define LPD7A400_CPLD_REV_REG (0x71400000)
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#define LPD7A400_CPLD_EXTGPIO_REG (0x71600000)
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#define LPD7A400_CPLD_GPIODATA_REG (0x71800000)
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#define LPD7A400_CPLD_GPIODIR_REG (0x71a00000)
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#define LPD7A400_CPLD_REGPTR (volatile u8*)
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/* Card Engine Control Register (section 3.1.2) */
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#define CECTL_SWINT (0x80) /* Software settable interrupt source
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(routed to uP PF3)
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0 = generate interrupt, 1 = do not */
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#define CECTL_OCMSK (0x40) /* USB1 connection interrupt mask
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0 = not masked, 1 = masked */
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#define CECTL_PDRV (0x20) /* PCC_nDRV output
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0 = active, 1 = inactive */
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#define CECTL_USB1C (0x10) /* USB1 connection interrupt
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0 = active, 1 = inactive */
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#define CECTL_USB1P (0x08) /* USB1 Power enable
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0 = enabled, 1 = disabled */
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#define CECTL_AWKP (0x04) /* Auto-Wakeup enable
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0 = enabled, 1 = disabled */
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#define CECTL_LCDV (0x02) /* LCD VEE enable
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0 = disabled, 1 = enabled */
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#define CECTL_WLPE (0x01) /* Wired LAN power enable
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0 = enabled, 1 = disabled */
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/* SPI Control Register (section 3.1.5) */
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#define SPICTL_SPLD (0x20) /* SPI load (R)
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0 = data reg. has not been loaded, shift
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count has not been reset
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1 = data reg. loaded, shift count reset */
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#define SPICTL_SPST (0x10) /* SPI start (RW)
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0 = don't load data reg. and reset shift count
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1 = ready to load data reg and reset shift count */
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#define SPICTL_SPDN (0x08) /* SPI done (R)
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0 = not done
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1 = access done */
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#define SPICTL_SPRW (0x04) /* SPI read/write (RW)
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0 = SPI write access
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1 = SPI read access */
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#define SPICTL_STCS (0x02) /* SPI touch chip select (RW)
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0 = not selected
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1 = selected */
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#define SPICTL_SCCS (0x01) /* SPI CODEC chip select (RW) {not used}
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0 = not selected
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1 = selected */
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/* EEPROM SPI Interface Register (section 3.1.6) */
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#define EEPSPI_EECS (0x08) /* EEPROM chip select (RW)
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0 = not selected
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1 = selected */
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#define EEPSPI_EECK (0x04) /* EEPROM SPI clock (RW) */
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#define EEPSPI_EETX (0x02) /* EEPROM SPI tx data (RW) */
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#define EEPSPI_EERX (0x01) /* EEPROM SPI rx data (R) */
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/* Interrupt/Mask Register (section 3.1.7) */
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#define INTMASK_CMSK (0x80) /* CPLD_nIRQD interrupt mask (RW)
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0 = not masked
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1 = masked */
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#define INTMASK_CIRQ (0x40) /* interrupt signal to CPLD (R)
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0 = interrupt active
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1 = no interrupt */
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#define INTMASK_PIRQ (0x10) /* legacy, no effect */
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#define INTMASK_TMSK (0x08) /* Touch chip interrupt mask (RW)
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0 = not masked
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1 = masked */
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#define INTMASK_WMSK (0x04) /* Wired LAN interrupt mask (RW)
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0 = not masked
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1 = masked */
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#define INTMASK_TIRQ (0x02) /* Touch chip interrupt request (R)
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0 = interrupt active
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1 = no interrupt */
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#define INTMASK_WIRQ (0x01) /* Wired LAN interrupt request (R)
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0 = interrupt active
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1 = no interrupt */
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/* Mode Register (section 3.1.8) */
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#define MODE_VS1 (0x80) /* PCMCIA Voltage Sense 1 input (PCC_VS1) (R)
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0 = active slot VS1 pin is low
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1 = active slot VS1 pin is high */
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#define MODE_CD2 (0x40) /* PCMCIA Card Detect 2 input (PCC_nCD2) (R)
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0 = active slot CD2 is low
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1 = active slot CD2 is high */
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#define MODE_IOIS16 (0x20) /* PCMCIA IOIS16 input (PCC_nIOIS16) (R)
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0 = 16 bit access area
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1 = 8 bit access area */
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#define MODE_CD1 (0x10) /* PCMCIA Card Detect 1 input (PCC_nCD1) (R)
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0 = active slot CD1 is low
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1 = active slot CD1 is high */
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#define MODE_upMODE3 (0x08) /* Mode Pin 3 (R)
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0 = off-board boot device
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1 = on-board boot device (flash) */
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#define MODE_upMODE2 (0x04) /* Mode Pin 2 (R) (LH7A400 Little Endian only)
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0 = big endian
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1 = little endian */
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#define MODE_upMODE1 (0x02) /* Mode Pin 1 and Mode Pin 2 (R) */
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#define MODE_upMODE0 (0x01) /* - bus width at boot */
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/* Flash Register (section 3.1.9) */
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#define FLASH_FPOP (0x08) /* Flash populated (RW)
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0 = populated, 1 = not */
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#define FLASH_FST2 (0x04) /* Flash status (R) (RY/BY# pin for upper 16 bit chip
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0 = busy, 1 = ready */
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#define FLASH_FST1 (0x02) /* Flash status (R) (RY/BY# pin for lower 16 bit chip
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0 = busy, 1 = ready */
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#define FLASH_FPEN (0x01) /* Flash program enable (RW)
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0 = flash write protected
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1 = programming enabled */
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/* Power Management Register (section 3.1.10)
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* - when either of these is low an unmaskable interrupt to cpu
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* is generated
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*/
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#define PWRMG_STBY (0x10) /* state of nSTANDBY signal to CPLD (R)
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0 = low, 1 = high */
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#define PWRMG_SPND (0x04) /* state of nSUSPEND signal to CPLD (R)
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0 = low, 1 = high */
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/* Extended GPIO Register (section 3.1.12) */
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#define EXTGPIO_STATUS1 (0x04) /* Status 1 output (RW) (uP_STATUS_1)
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0 = set pin low, 1 = set pin high */
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#define EXTGPIO_STATUS2 (0x02) /* Status 2 output (RW) (uP_STATUS_2)
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0 = set pin low, 1 = set pin high */
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#define EXTGPIO_GPIO1 (0x01) /* General purpose output (RW) (CPLD_GPIO_1)
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0 = set pin low, 1 = set pin high */
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/* GPIO Data Register (section 3.1.13) */
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#define GPIODATA_GPIO2 (0x01) /* General purpose input/output (RW) (CPLD_GPIO_2)
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0 = set low (output) / read low (input)
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1 = set high (output) / read high (input) */
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/* GPIO Direction Register (section 3.1.14) */
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#define GPIODIR_GPDR0 (0x01) /* GPIO2 direction (RW)
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0 = output, 1 = input */
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#endif /* __LH7A400_H__ */
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