mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-23 11:33:32 +00:00
fa2f20d3c0
Add i.MX7ULP dtsi file. Add clock and pinfun header files. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefano Babic <sbabic@denx.de>
161 lines
4.8 KiB
C
161 lines
4.8 KiB
C
/*
|
|
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
* published by the Free Software Foundation.
|
|
*
|
|
*/
|
|
|
|
#ifndef __DT_BINDINGS_CLOCK_IMX7ULP_H
|
|
#define __DT_BINDINGS_CLOCK_IMX7ULP_H
|
|
|
|
#define IMX7ULP_CLK_DUMMY 0
|
|
#define IMX7ULP_CLK_CKIL 1
|
|
#define IMX7ULP_CLK_OSC 2
|
|
#define IMX7ULP_CLK_FIRC 3
|
|
|
|
/* SCG1 */
|
|
#define IMX7ULP_CLK_SPLL_PRE_SEL 4
|
|
#define IMX7ULP_CLK_SPLL_PRE_DIV 5
|
|
#define IMX7ULP_CLK_SPLL 6
|
|
#define IMX7ULP_CLK_SPLL_POST_DIV1 7
|
|
#define IMX7ULP_CLK_SPLL_POST_DIV2 8
|
|
#define IMX7ULP_CLK_SPLL_PFD0 9
|
|
#define IMX7ULP_CLK_SPLL_PFD1 10
|
|
#define IMX7ULP_CLK_SPLL_PFD2 11
|
|
#define IMX7ULP_CLK_SPLL_PFD3 12
|
|
#define IMX7ULP_CLK_SPLL_PFD_SEL 13
|
|
#define IMX7ULP_CLK_SPLL_SEL 14
|
|
#define IMX7ULP_CLK_APLL_PRE_SEL 15
|
|
#define IMX7ULP_CLK_APLL_PRE_DIV 16
|
|
#define IMX7ULP_CLK_APLL 17
|
|
#define IMX7ULP_CLK_APLL_POST_DIV1 18
|
|
#define IMX7ULP_CLK_APLL_POST_DIV2 19
|
|
#define IMX7ULP_CLK_APLL_PFD0 20
|
|
#define IMX7ULP_CLK_APLL_PFD1 21
|
|
#define IMX7ULP_CLK_APLL_PFD2 22
|
|
#define IMX7ULP_CLK_APLL_PFD3 23
|
|
#define IMX7ULP_CLK_APLL_PFD_SEL 24
|
|
#define IMX7ULP_CLK_APLL_SEL 25
|
|
#define IMX7ULP_CLK_UPLL 26
|
|
#define IMX7ULP_CLK_SYS_SEL 27
|
|
#define IMX7ULP_CLK_CORE_DIV 28
|
|
#define IMX7ULP_CLK_BUS_DIV 29
|
|
#define IMX7ULP_CLK_PLAT_DIV 30
|
|
#define IMX7ULP_CLK_DDR_SEL 31
|
|
#define IMX7ULP_CLK_DDR_DIV 32
|
|
#define IMX7ULP_CLK_NIC_SEL 33
|
|
#define IMX7ULP_CLK_NIC0_DIV 34
|
|
#define IMX7ULP_CLK_GPU_DIV 35
|
|
#define IMX7ULP_CLK_NIC1_DIV 36
|
|
#define IMX7ULP_CLK_NIC1_BUS_DIV 37
|
|
#define IMX7ULP_CLK_NIC1_EXT_DIV 38
|
|
|
|
/* PCG2 */
|
|
#define IMX7ULP_CLK_DMA1 39
|
|
#define IMX7ULP_CLK_RGPIO2P1 40
|
|
#define IMX7ULP_CLK_FLEXBUS 41
|
|
#define IMX7ULP_CLK_SEMA42_1 42
|
|
#define IMX7ULP_CLK_DMA_MUX1 43
|
|
#define IMX7ULP_CLK_SNVS 44
|
|
#define IMX7ULP_CLK_CAAM 45
|
|
#define IMX7ULP_CLK_LPTPM4 46
|
|
#define IMX7ULP_CLK_LPTPM5 47
|
|
#define IMX7ULP_CLK_LPIT1 48
|
|
#define IMX7ULP_CLK_LPSPI2 49
|
|
#define IMX7ULP_CLK_LPSPI3 50
|
|
#define IMX7ULP_CLK_LPI2C4 51
|
|
#define IMX7ULP_CLK_LPI2C5 52
|
|
#define IMX7ULP_CLK_LPUART4 53
|
|
#define IMX7ULP_CLK_LPUART5 54
|
|
#define IMX7ULP_CLK_FLEXIO1 55
|
|
#define IMX7ULP_CLK_USB0 56
|
|
#define IMX7ULP_CLK_USB1 57
|
|
#define IMX7ULP_CLK_USB_PHY 58
|
|
#define IMX7ULP_CLK_USB_PL301 59
|
|
#define IMX7ULP_CLK_USDHC0 60
|
|
#define IMX7ULP_CLK_USDHC1 61
|
|
#define IMX7ULP_CLK_WDG1 62
|
|
#define IMX7ULP_CLK_WDG2 63
|
|
|
|
/* PCG3 */
|
|
#define IMX7ULP_CLK_LPTPM6 64
|
|
#define IMX7ULP_CLK_LPTPM7 65
|
|
#define IMX7ULP_CLK_LPI2C6 66
|
|
#define IMX7ULP_CLK_LPI2C7 67
|
|
#define IMX7ULP_CLK_LPUART6 68
|
|
#define IMX7ULP_CLK_LPUART7 69
|
|
#define IMX7ULP_CLK_VIU 70
|
|
#define IMX7ULP_CLK_DSI 71
|
|
#define IMX7ULP_CLK_LCDIF 72
|
|
#define IMX7ULP_CLK_MMDC 73
|
|
#define IMX7ULP_CLK_PCTLC 74
|
|
#define IMX7ULP_CLK_PCTLD 75
|
|
#define IMX7ULP_CLK_PCTLE 76
|
|
#define IMX7ULP_CLK_PCTLF 77
|
|
#define IMX7ULP_CLK_GPU3D 78
|
|
#define IMX7ULP_CLK_GPU2D 79
|
|
|
|
#define IMX7ULP_CLK_MIPI_PLL 80
|
|
#define IMX7ULP_CLK_SIRC 81
|
|
|
|
#define IMX7ULP_CLK_SCG1_CLKOUT 82
|
|
|
|
#define IMX7ULP_CLK_END 83
|
|
|
|
/*cm4 clocks*/
|
|
#define IMX7ULP_CM4_CLK_DUMMY 0
|
|
#define IMX7ULP_CM4_CLK_CKIL 1
|
|
#define IMX7ULP_CM4_CLK_OSC 2
|
|
#define IMX7ULP_CM4_CLK_FIRC 3
|
|
#define IMX7ULP_CM4_CLK_SIRC 4
|
|
|
|
/* SCG0 */
|
|
#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_SEL 5
|
|
#define IMX7ULP_CM4_CLK_SPLL_VCO_PRE_DIV 6
|
|
#define IMX7ULP_CM4_CLK_SPLL 7
|
|
#define IMX7ULP_CM4_CLK_SPLL_VCO 8
|
|
#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV1 9
|
|
#define IMX7ULP_CM4_CLK_SPLL_VCO_POST_DIV2 10
|
|
#define IMX7ULP_CM4_CLK_SPLL_PFD0 11
|
|
#define IMX7ULP_CM4_CLK_SPLL_PFD1 12
|
|
#define IMX7ULP_CM4_CLK_SPLL_PFD2 13
|
|
#define IMX7ULP_CM4_CLK_SPLL_PFD3 14
|
|
#define IMX7ULP_CM4_CLK_SPLL_PFD_SEL 15
|
|
#define IMX7ULP_CM4_CLK_SPLL_PFD 16
|
|
#define IMX7ULP_CM4_CLK_SPLL_SEL 17
|
|
#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_SEL 18
|
|
#define IMX7ULP_CM4_CLK_APLL_VCO_PRE_DIV 19
|
|
#define IMX7ULP_CM4_CLK_APLL 20
|
|
#define IMX7ULP_CM4_CLK_APLL_VCO 21
|
|
#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV1 22
|
|
#define IMX7ULP_CM4_CLK_APLL_VCO_POST_DIV2 23
|
|
#define IMX7ULP_CM4_CLK_APLL_PFD0 24
|
|
#define IMX7ULP_CM4_CLK_APLL_PFD1 25
|
|
#define IMX7ULP_CM4_CLK_APLL_PFD2 26
|
|
#define IMX7ULP_CM4_CLK_APLL_PFD3 27
|
|
#define IMX7ULP_CM4_CLK_APLL_PFD_SEL 28
|
|
#define IMX7ULP_CM4_CLK_APLL_PFD 29
|
|
#define IMX7ULP_CM4_CLK_APLL_SEL 30
|
|
#define IMX7ULP_CM4_CLK_APLL_PFD0_PRE_DIV 31
|
|
#define IMX7ULP_CM4_CLK_SYS_SEL 32
|
|
#define IMX7ULP_CM4_CLK_CORE_DIV 33
|
|
#define IMX7ULP_CM4_CLK_BUS_DIV 34
|
|
#define IMX7ULP_CM4_CLK_PLAT_DIV 35
|
|
#define IMX7ULP_CM4_CLK_SLOW_DIV 36
|
|
|
|
#define IMX7ULP_CM4_CLK_SAI0_SEL 37
|
|
#define IMX7ULP_CM4_CLK_SAI0_DIV 38
|
|
#define IMX7ULP_CM4_CLK_SAI0_ROOT 39
|
|
#define IMX7ULP_CM4_CLK_SAI0_IPG 40
|
|
#define IMX7ULP_CM4_CLK_SAI1_SEL 41
|
|
#define IMX7ULP_CM4_CLK_SAI1_DIV 42
|
|
#define IMX7ULP_CM4_CLK_SAI1_ROOT 43
|
|
#define IMX7ULP_CM4_CLK_SAI1_IPG 44
|
|
|
|
#define IMX7ULP_CLK_SCG0_CLKOUT 45
|
|
|
|
#define IMX7ULP_CM4_CLK_END 46
|
|
|
|
#endif /* __DT_BINDINGS_CLOCK_IMX7ULP_H */
|