mirror of
https://github.com/AsahiLinux/u-boot
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83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
130 lines
3.4 KiB
C
130 lines
3.4 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2014, STMicroelectronics - All Rights Reserved
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* Author(s): Vikas Manocha, <vikas.manocha@st.com> for STMicroelectronics.
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*/
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#ifndef _STV0991_CGU_H
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#define _STV0991_CGU_H
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struct stv0991_cgu_regs {
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u32 cpu_freq; /* offset 0x0 */
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u32 icn2_freq; /* offset 0x4 */
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u32 dma_freq; /* offset 0x8 */
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u32 isp_freq; /* offset 0xc */
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u32 h264_freq; /* offset 0x10 */
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u32 osif_freq; /* offset 0x14 */
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u32 ren_freq; /* offset 0x18 */
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u32 tim_freq; /* offset 0x1c */
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u32 sai_freq; /* offset 0x20 */
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u32 eth_freq; /* offset 0x24 */
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u32 i2c_freq; /* offset 0x28 */
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u32 spi_freq; /* offset 0x2c */
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u32 uart_freq; /* offset 0x30 */
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u32 qspi_freq; /* offset 0x34 */
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u32 sdio_freq; /* offset 0x38 */
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u32 usi_freq; /* offset 0x3c */
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u32 can_line_freq; /* offset 0x40 */
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u32 debug_freq; /* offset 0x44 */
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u32 trace_freq; /* offset 0x48 */
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u32 stm_freq; /* offset 0x4c */
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u32 eth_ctrl; /* offset 0x50 */
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u32 reserved[3]; /* offset 0x54 */
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u32 osc_ctrl; /* offset 0x60 */
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u32 pll1_ctrl; /* offset 0x64 */
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u32 pll1_freq; /* offset 0x68 */
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u32 pll1_fract; /* offset 0x6c */
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u32 pll1_spread; /* offset 0x70 */
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u32 pll1_status; /* offset 0x74 */
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u32 pll2_ctrl; /* offset 0x78 */
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u32 pll2_freq; /* offset 0x7c */
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u32 pll2_fract; /* offset 0x80 */
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u32 pll2_spread; /* offset 0x84 */
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u32 pll2_status; /* offset 0x88 */
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u32 cgu_enable_1; /* offset 0x8c */
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u32 cgu_enable_2; /* offset 0x90 */
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u32 cgu_isp_pulse; /* offset 0x94 */
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u32 cgu_h264_pulse; /* offset 0x98 */
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u32 cgu_osif_pulse; /* offset 0x9c */
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u32 cgu_ren_pulse; /* offset 0xa0 */
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};
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/* CGU Timer */
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#define CLK_TMR_OSC 0
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#define CLK_TMR_MCLK 1
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#define CLK_TMR_PLL1 2
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#define CLK_TMR_PLL2 3
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#define MDIV_SHIFT_TMR 3
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#define DIV_SHIFT_TMR 6
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#define TIMER1_CLK_CFG (0 << DIV_SHIFT_TMR \
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| 0 << MDIV_SHIFT_TMR | CLK_TMR_MCLK)
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/* Clock Enable/Disable */
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#define TIMER1_CLK_EN (1 << 15)
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/* CGU Uart config */
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#define CLK_UART_MCLK 0
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#define CLK_UART_PLL1 1
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#define CLK_UART_PLL2 2
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#define MDIV_SHIFT_UART 3
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#define DIV_SHIFT_UART 6
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#define UART_CLK_CFG (4 << DIV_SHIFT_UART \
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| 1 << MDIV_SHIFT_UART | CLK_UART_MCLK)
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/* CGU Ethernet clock config */
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#define CLK_ETH_MCLK 0
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#define CLK_ETH_PLL1 1
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#define CLK_ETH_PLL2 2
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#define MDIV_SHIFT_ETH 3
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#define DIV_SHIFT_ETH 6
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#define DIV_ETH_125 9
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#define DIV_ETH_50 12
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#define DIV_ETH_P2P 15
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#define ETH_CLK_CFG (4 << DIV_ETH_P2P | 4 << DIV_ETH_50 \
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| 1 << DIV_ETH_125 \
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| 0 << DIV_SHIFT_ETH \
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| 3 << MDIV_SHIFT_ETH | CLK_ETH_PLL1)
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/* CGU Ethernet control */
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#define ETH_CLK_TX_EXT_PHY 0
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#define ETH_CLK_TX_125M 1
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#define ETH_CLK_TX_25M 2
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#define ETH_CLK_TX_2M5 3
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#define ETH_CLK_TX_DIS 7
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#define ETH_CLK_RX_EXT_PHY 0
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#define ETH_CLK_RX_25M 1
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#define ETH_CLK_RX_2M5 2
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#define ETH_CLK_RX_DIS 3
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#define RX_CLK_SHIFT 3
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#define ETH_CLK_MASK ~(0x1F)
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#define ETH_PHY_MODE_GMII 0
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#define ETH_PHY_MODE_RMII 1
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#define ETH_PHY_CLK_DIS 1
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#define ETH_CLK_CTRL (ETH_CLK_RX_EXT_PHY << RX_CLK_SHIFT \
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| ETH_CLK_TX_EXT_PHY)
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/* CGU qspi clock */
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#define DIV_HCLK1_SHIFT 9
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#define DIV_CRYP_SHIFT 6
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#define MDIV_QSPI_SHIFT 3
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#define CLK_QSPI_OSC 0
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#define CLK_QSPI_MCLK 1
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#define CLK_QSPI_PLL1 2
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#define CLK_QSPI_PLL2 3
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#define QSPI_CLK_CTRL (3 << DIV_HCLK1_SHIFT \
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| 1 << DIV_CRYP_SHIFT \
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| 0 << MDIV_QSPI_SHIFT \
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| CLK_QSPI_OSC)
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#endif
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