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953bb4c3ce
Add support for MediaTek MT8512 SoC. This include the file that will initialize the SoC after boot and its device tree. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
115 lines
No EOL
2.8 KiB
Text
115 lines
No EOL
2.8 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2019 MediaTek Inc.
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* Author: Mingming Lee <mingming.lee@mediatek.com>
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*
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*/
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#include <dt-bindings/clock/mt8512-clk.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "mediatek,mt8512";
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interrupt-parent = <&sysirq>;
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#address-cells = <1>;
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#size-cells = <1>;
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0xc000000 0x40000>, /* GICD */
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<0xc080000 0x200000>; /* GICR */
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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topckgen: clock-controller@10000000 {
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compatible = "mediatek,mt8512-topckgen";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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topckgen_cg: clock-controller-cg@10000000 {
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compatible = "mediatek,mt8512-topckgen-cg";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: clock-controller@10001000 {
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compatible = "mediatek,mt8512-infracfg";
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reg = <0x10001000 0x1000>;
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#clock-cells = <1>;
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};
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pinctrl: pinctrl@10005000 {
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compatible = "mediatek,mt8512-pinctrl";
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reg = <0x10005000 0x1000>;
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gpio: gpio-controller {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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watchdog0: watchdog@10007000 {
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compatible = "mediatek,wdt";
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reg = <0x10007000 0x1000>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>;
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#reset-cells = <1>;
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status = "disabled";
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timeout-sec = <60>;
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reset-on-timeout;
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};
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timer0: apxgpt@10008000 {
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compatible = "mediatek,timer";
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reg = <0x10008000 0x1000>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYS_26M_D2>,
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<&topckgen CLK_TOP_CLK32K>,
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<&infracfg CLK_INFRA_APXGPT>;
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clock-names = "clk13m",
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"clk32k",
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"bus";
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};
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apmixedsys: clock-controller@1000c000 {
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compatible = "mediatek,mt8512-apmixedsys";
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reg = <0x1000c000 0x1000>;
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#clock-cells = <1>;
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};
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sysirq: interrupt-controller@10200a80 {
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compatible = "mediatek,sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10200a80 0x50>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,hsuart";
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reg = <0x11002000 0x1000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_CLK26M>,
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<&infracfg CLK_INFRA_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt8512-mmc";
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reg = <0x11230000 0x1000>,
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<0x11cd0000 0x1000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
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<&infracfg CLK_INFRA_MSDC0>,
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<&infracfg CLK_INFRA_MSDC0_SRC>;
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clock-names = "source", "hclk", "source_cg";
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status = "disabled";
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};
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}; |