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267c5146d3
When CONFIG_DM_ETH is enabled DPAA2 network interfaces will now probe based on DTS nodes with the "fsl,qoriq-mc-dpmac" compatible. In this case, transform the ldpaa_eth driver into a UCLASS_ETH driver and reuse the _open()/_tx()/_stop() functions already inplemented. For the moment, the ldpaa_eth driver will support both configurations: with or without CONFIG_DM_ETH enabled. Any 'struct eth_device' occurrence now has a matching 'struct udevice' made mutually exclusive based on the state of CONFIG_DM_ETH. Signed-off-by: Florin Laurentiu Chiculita <florinlaurentiu.chiculita@nxp.com> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
156 lines
4.5 KiB
C
156 lines
4.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright 2014-2016 Freescale Semiconductor, Inc.
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* Copyright 2017 NXP
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*/
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#ifndef __LDPAA_ETH_H
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#define __LDPAA_ETH_H
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#include <linux/netdevice.h>
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#include <fsl-mc/fsl_mc.h>
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#include <fsl-mc/fsl_dpaa_fd.h>
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#include <fsl-mc/fsl_dprc.h>
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#include <fsl-mc/fsl_dpni.h>
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#include <fsl-mc/fsl_dpbp.h>
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#include <fsl-mc/fsl_dpio.h>
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#include <fsl-mc/fsl_qbman_portal.h>
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#include <fsl-mc/fsl_mc_private.h>
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enum ldpaa_eth_type {
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LDPAA_ETH_1G_E,
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LDPAA_ETH_10G_E,
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};
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/* Arbitrary values for now, but we'll need to tune */
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#define LDPAA_ETH_NUM_BUFS (7 * 7)
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#define LDPAA_ETH_REFILL_THRESH (LDPAA_ETH_NUM_BUFS/2)
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#define LDPAA_ETH_RX_BUFFER_SIZE 2048
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/* Hardware requires alignment for buffer address and length: 256-byte
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* for ingress, 64-byte for egress. Using 256 for both.
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*/
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#define LDPAA_ETH_BUF_ALIGN 256
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/* So far we're only accomodating a skb backpointer in the frame's
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* software annotation, but the hardware options are either 0 or 64.
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*/
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#define LDPAA_ETH_SWA_SIZE 64
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/* Annotation valid bits in FD FRC */
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#define LDPAA_FD_FRC_FASV 0x8000
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#define LDPAA_FD_FRC_FAEADV 0x4000
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#define LDPAA_FD_FRC_FAPRV 0x2000
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#define LDPAA_FD_FRC_FAIADV 0x1000
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#define LDPAA_FD_FRC_FASWOV 0x0800
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#define LDPAA_FD_FRC_FAICFDV 0x0400
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/* Annotation bits in FD CTRL */
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#define LDPAA_FD_CTRL_ASAL 0x00020000 /* ASAL = 128 */
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#define LDPAA_FD_CTRL_PTA 0x00800000
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#define LDPAA_FD_CTRL_PTV1 0x00400000
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/* TODO: we may want to move this and other WRIOP related defines
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* to a separate header
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*/
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/* Frame annotation status */
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struct ldpaa_fas {
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u8 reserved;
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u8 ppid;
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__le16 ifpid;
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__le32 status;
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} __packed;
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/* Debug frame, otherwise supposed to be discarded */
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#define LDPAA_ETH_FAS_DISC 0x80000000
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/* MACSEC frame */
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#define LDPAA_ETH_FAS_MS 0x40000000
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#define LDPAA_ETH_FAS_PTP 0x08000000
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/* Ethernet multicast frame */
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#define LDPAA_ETH_FAS_MC 0x04000000
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/* Ethernet broadcast frame */
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#define LDPAA_ETH_FAS_BC 0x02000000
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#define LDPAA_ETH_FAS_KSE 0x00040000
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#define LDPAA_ETH_FAS_EOFHE 0x00020000
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#define LDPAA_ETH_FAS_MNLE 0x00010000
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#define LDPAA_ETH_FAS_TIDE 0x00008000
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#define LDPAA_ETH_FAS_PIEE 0x00004000
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/* Frame length error */
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#define LDPAA_ETH_FAS_FLE 0x00002000
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/* Frame physical error; our favourite pastime */
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#define LDPAA_ETH_FAS_FPE 0x00001000
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#define LDPAA_ETH_FAS_PTE 0x00000080
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#define LDPAA_ETH_FAS_ISP 0x00000040
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#define LDPAA_ETH_FAS_PHE 0x00000020
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#define LDPAA_ETH_FAS_BLE 0x00000010
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/* L3 csum validation performed */
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#define LDPAA_ETH_FAS_L3CV 0x00000008
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/* L3 csum error */
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#define LDPAA_ETH_FAS_L3CE 0x00000004
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/* L4 csum validation performed */
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#define LDPAA_ETH_FAS_L4CV 0x00000002
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/* L4 csum error */
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#define LDPAA_ETH_FAS_L4CE 0x00000001
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/* These bits always signal errors */
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#define LDPAA_ETH_RX_ERR_MASK (LDPAA_ETH_FAS_DISC | \
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LDPAA_ETH_FAS_KSE | \
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LDPAA_ETH_FAS_EOFHE | \
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LDPAA_ETH_FAS_MNLE | \
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LDPAA_ETH_FAS_TIDE | \
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LDPAA_ETH_FAS_PIEE | \
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LDPAA_ETH_FAS_FLE | \
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LDPAA_ETH_FAS_FPE | \
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LDPAA_ETH_FAS_PTE | \
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LDPAA_ETH_FAS_ISP | \
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LDPAA_ETH_FAS_PHE | \
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LDPAA_ETH_FAS_BLE | \
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LDPAA_ETH_FAS_L3CE | \
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LDPAA_ETH_FAS_L4CE)
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/* Unsupported features in the ingress */
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#define LDPAA_ETH_RX_UNSUPP_MASK LDPAA_ETH_FAS_MS
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/* TODO trim down the bitmask; not all of them apply to Tx-confirm */
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#define LDPAA_ETH_TXCONF_ERR_MASK (LDPAA_ETH_FAS_KSE | \
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LDPAA_ETH_FAS_EOFHE | \
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LDPAA_ETH_FAS_MNLE | \
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LDPAA_ETH_FAS_TIDE)
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struct ldpaa_eth_priv {
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#ifdef CONFIG_DM_ETH
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struct phy_device *phy;
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int phy_mode;
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bool started;
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#else
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struct eth_device *net_dev;
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#endif
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uint32_t dpmac_id;
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uint16_t dpmac_handle;
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uint16_t tx_data_offset;
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uint32_t rx_dflt_fqid;
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uint16_t tx_qdid;
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uint16_t tx_flow_id;
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enum ldpaa_eth_type type; /* 1G or 10G ethernet */
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};
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struct dprc_endpoint dpmac_endpoint;
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struct dprc_endpoint dpni_endpoint;
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extern struct fsl_mc_io *dflt_mc_io;
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extern struct fsl_dpbp_obj *dflt_dpbp;
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extern struct fsl_dpio_obj *dflt_dpio;
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extern struct fsl_dpni_obj *dflt_dpni;
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extern uint16_t dflt_dprc_handle;
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static void ldpaa_dpbp_drain_cnt(int count);
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static void ldpaa_dpbp_drain(void);
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static int ldpaa_dpbp_seed(uint16_t bpid);
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static void ldpaa_dpbp_free(void);
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static int ldpaa_dpni_setup(struct ldpaa_eth_priv *priv);
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static int ldpaa_dpbp_setup(void);
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static int ldpaa_dpni_bind(struct ldpaa_eth_priv *priv);
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static int ldpaa_dpmac_setup(struct ldpaa_eth_priv *priv);
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static int ldpaa_dpmac_bind(struct ldpaa_eth_priv *priv);
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#endif /* __LDPAA_H */
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