mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-30 00:21:06 +00:00
6c8945ec41
Add macro QIXIS_LBMAP_EMMC, QIXIS_LBMAP_IFC, QIXIS_RCW_SRC_IFC, QIXIS_RCW_SRC_EMMC to enable IFC and eMMC as boot sources for qixis commands. Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> [YS: Modify subject and add commit message] Reviewed-by: York Sun <york.sun@nxp.com>
477 lines
15 KiB
C
477 lines
15 KiB
C
/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1088A_RDB_H
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#define __LS1088A_RDB_H
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#include "ls1088a_common.h"
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#ifndef SPL_NO_BOARDINFO
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#define CONFIG_DISPLAY_BOARDINFO_LATE
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#endif
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#define CONFIG_MISC_INIT_R
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#if defined(CONFIG_QSPI_BOOT)
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#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
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#define CONFIG_ENV_SECT_SIZE 0x40000
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#elif defined(CONFIG_SD_BOOT)
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#define CONFIG_ENV_OFFSET (3 * 1024 * 1024)
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#define CONFIG_SYS_MMC_ENV_DEV 0
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#define CONFIG_ENV_SIZE 0x2000
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#else
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#define CONFIG_ENV_IS_IN_FLASH
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#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x300000)
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#define CONFIG_ENV_SECT_SIZE 0x20000
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#define CONFIG_ENV_SIZE 0x20000
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#endif
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#ifndef CONFIG_SPL_BUILD
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#define CONFIG_QIXIS_I2C_ACCESS
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#endif
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#define SYS_NO_FLASH
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#undef CONFIG_CMD_IMLS
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#endif
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#define CONFIG_SYS_CLK_FREQ 100000000
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#define CONFIG_DDR_CLK_FREQ 100000000
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#define COUNTER_FREQUENCY_REAL 25000000 /* 25MHz */
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#define COUNTER_FREQUENCY 25000000 /* 25MHz */
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#define CONFIG_DDR_SPD
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#ifdef CONFIG_EMU
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#define CONFIG_SYS_FSL_DDR_EMU
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#define CONFIG_SYS_MXC_I2C1_SPEED 40000000
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#define CONFIG_SYS_MXC_I2C2_SPEED 40000000
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#else
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#define CONFIG_DDR_ECC
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#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
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#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
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#endif
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#define SPD_EEPROM_ADDRESS 0x51
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#define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD on I2C bus 0 */
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#define CONFIG_DIMM_SLOTS_PER_CTLR 1
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#if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
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#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
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#define CONFIG_SYS_NOR_AMASK_EARLY IFC_AMASK(64 * 1024 * 1024)
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#define CONFIG_SYS_NOR0_CSPR \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR0_CSPR_EARLY \
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(CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY) | \
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CSPR_PORT_SIZE_16 | \
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CSPR_MSEL_NOR | \
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CSPR_V)
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#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(6)
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#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x1) | \
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FTIM0_NOR_TEADC(0x1) | \
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FTIM0_NOR_TEAHC(0x1))
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#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1) | \
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FTIM1_NOR_TRAD_NOR(0x1))
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#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x0) | \
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FTIM2_NOR_TCH(0x0) | \
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FTIM2_NOR_TWP(0x1))
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#define CONFIG_SYS_NOR_FTIM3 0x04000000
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#define CONFIG_SYS_IFC_CCR 0x01000000
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#ifndef SYS_NO_FLASH
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#define CONFIG_FLASH_CFI_DRIVER
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#define CONFIG_SYS_FLASH_CFI
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#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
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#define CONFIG_SYS_FLASH_QUIET_TEST
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#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
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#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
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#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
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#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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#define CONFIG_SYS_FLASH_EMPTY_INFO
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#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
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#endif
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#endif
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#ifndef SPL_NO_IFC
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#define CONFIG_NAND_FSL_IFC
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#endif
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#define CONFIG_SYS_NAND_MAX_ECCPOS 256
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#define CONFIG_SYS_NAND_MAX_OOBFREE 2
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#define CONFIG_SYS_NAND_CSPR_EXT (0x0)
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#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
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| CSPR_MSEL_NAND /* MSEL = NAND */ \
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| CSPR_V)
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#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64 * 1024)
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#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
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| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
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| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
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| CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
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| CSOR_NAND_PGS_2K /* Page Size = 2K */ \
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| CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
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| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
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#define CONFIG_SYS_NAND_ONFI_DETECTION
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/* ONFI NAND Flash mode0 Timing Params */
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#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
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FTIM0_NAND_TWP(0x18) | \
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FTIM0_NAND_TWCHT(0x07) | \
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FTIM0_NAND_TWH(0x0a))
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#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
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FTIM1_NAND_TWBE(0x39) | \
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FTIM1_NAND_TRR(0x0e) | \
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FTIM1_NAND_TRP(0x18))
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#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
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FTIM2_NAND_TREH(0x0a) | \
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FTIM2_NAND_TWHRE(0x1e))
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#define CONFIG_SYS_NAND_FTIM3 0x0
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#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
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#define CONFIG_SYS_MAX_NAND_DEVICE 1
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#define CONFIG_MTD_NAND_VERIFY_WRITE
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#define CONFIG_CMD_NAND
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#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
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#ifndef SPL_NO_QIXIS
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#define CONFIG_FSL_QIXIS
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#endif
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#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
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#define QIXIS_BRDCFG4_OFFSET 0x54
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#define QIXIS_LBMAP_SWITCH 2
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#define QIXIS_QMAP_MASK 0xe0
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#define QIXIS_QMAP_SHIFT 5
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#define QIXIS_LBMAP_MASK 0x1f
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#define QIXIS_LBMAP_SHIFT 5
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#define QIXIS_LBMAP_DFLTBANK 0x00
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#define QIXIS_LBMAP_ALTBANK 0x20
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#define QIXIS_LBMAP_SD 0x00
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#define QIXIS_LBMAP_EMMC 0x00
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#define QIXIS_LBMAP_SD_QSPI 0x00
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#define QIXIS_LBMAP_QSPI 0x00
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#define QIXIS_RCW_SRC_SD 0x40
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#define QIXIS_RCW_SRC_EMMC 0x41
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#define QIXIS_RCW_SRC_QSPI 0x62
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#define QIXIS_RST_CTL_RESET 0x31
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#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
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#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
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#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
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#define QIXIS_RST_FORCE_MEM 0x01
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#define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
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#define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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#define SYS_FPGA_CSPR_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
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| CSPR_PORT_SIZE_8 \
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| CSPR_MSEL_GPCM \
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| CSPR_V)
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#define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64*1024)
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#define CONFIG_SYS_FPGA_CSOR CSOR_GPCM_ADM_SHIFT(0)
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/* QIXIS Timing parameters*/
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#define SYS_FPGA_CS_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
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FTIM0_GPCM_TEADC(0x0e) | \
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FTIM0_GPCM_TEAHC(0x0e))
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#define SYS_FPGA_CS_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
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FTIM1_GPCM_TRAD(0x3f))
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#define SYS_FPGA_CS_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
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FTIM2_GPCM_TCH(0xf) | \
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FTIM2_GPCM_TWP(0x3E))
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#define SYS_FPGA_CS_FTIM3 0x0
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
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#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_FPGA_CSPR_EXT
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#define CONFIG_SYS_CSPR2 CONFIG_SYS_FPGA_CSPR
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#define CONFIG_SYS_CSPR2_FINAL SYS_FPGA_CSPR_FINAL
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#define CONFIG_SYS_AMASK2 CONFIG_SYS_FPGA_AMASK
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#define CONFIG_SYS_CSOR2 CONFIG_SYS_FPGA_CSOR
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#define CONFIG_SYS_CS2_FTIM0 SYS_FPGA_CS_FTIM0
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#define CONFIG_SYS_CS2_FTIM1 SYS_FPGA_CS_FTIM1
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#define CONFIG_SYS_CS2_FTIM2 SYS_FPGA_CS_FTIM2
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#define CONFIG_SYS_CS2_FTIM3 SYS_FPGA_CS_FTIM3
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#else
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#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
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#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR_EARLY
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#define CONFIG_SYS_CSPR0_FINAL CONFIG_SYS_NOR0_CSPR
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#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
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#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
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#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
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#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
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#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
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#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
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#endif
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#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
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#define I2C_MUX_CH_VOL_MONITOR 0xA
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/* Voltage monitor on channel 2*/
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#define I2C_VOL_MONITOR_ADDR 0x63
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#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
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#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
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#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
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#define I2C_SVDD_MONITOR_ADDR 0x4F
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#define CONFIG_VID_FLS_ENV "ls1088ardb_vdd_mv"
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#define CONFIG_VID
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/* The lowest and highest voltage allowed for LS1088ARDB */
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#define VDD_MV_MIN 819
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#define VDD_MV_MAX 1212
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#define CONFIG_VOL_MONITOR_LTC3882_SET
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#define CONFIG_VOL_MONITOR_LTC3882_READ
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/* PM Bus commands code for LTC3882*/
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#define PMBUS_CMD_PAGE 0x0
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#define PMBUS_CMD_READ_VOUT 0x8B
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#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
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#define PMBUS_CMD_VOUT_COMMAND 0x21
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#define PWM_CHANNEL0 0x0
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/*
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* I2C bus multiplexer
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*/
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#define I2C_MUX_PCA_ADDR_PRI 0x77
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#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
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#define I2C_RETIMER_ADDR 0x18
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#define I2C_MUX_CH_DEFAULT 0x8
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#define I2C_MUX_CH5 0xD
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#ifndef SPL_NO_RTC
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/*
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* RTC configuration
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*/
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#define RTC
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#define CONFIG_RTC_PCF8563 1
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#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
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#define CONFIG_CMD_DATE
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#endif
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/* EEPROM */
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#define CONFIG_ID_EEPROM
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#define CONFIG_SYS_I2C_EEPROM_NXID
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#define CONFIG_SYS_EEPROM_BUS_NUM 0
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#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
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#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
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#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
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#ifndef SPL_NO_QSPI
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/* QSPI device */
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#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
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#define CONFIG_FSL_QSPI
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#define FSL_QSPI_FLASH_SIZE (1 << 26)
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#define FSL_QSPI_FLASH_NUM 2
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#endif
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#endif
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#define CONFIG_CMD_MEMINFO
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#define CONFIG_CMD_MEMTEST
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#define CONFIG_SYS_MEMTEST_START 0x80000000
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#define CONFIG_SYS_MEMTEST_END 0x9fffffff
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#ifdef CONFIG_SPL_BUILD
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
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#else
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#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
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#endif
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#define CONFIG_FSL_MEMAC
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#ifndef SPL_NO_ENV
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/* Initial environment variables */
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#if defined(CONFIG_QSPI_BOOT)
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#define MC_INIT_CMD \
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"mcinitcmd=sf probe 0:0;sf read 0x80000000 0xA00000 0x100000;" \
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"sf read 0x80100000 0xE00000 0x100000;" \
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"env exists secureboot && " \
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"sf read 0x80700000 0x700000 0x40000 && " \
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"sf read 0x80740000 0x740000 0x40000 && " \
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"esbc_validate 0x80700000 && " \
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"esbc_validate 0x80740000 ;" \
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"fsl_mc start mc 0x80000000 0x80100000\0" \
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"mcmemsize=0x70000000\0"
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#elif defined(CONFIG_SD_BOOT)
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#define MC_INIT_CMD \
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"mcinitcmd=mmcinfo;mmc read 0x80000000 0x5000 0x800;" \
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"mmc read 0x80100000 0x7000 0x800;" \
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"env exists secureboot && " \
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"mmc read 0x80700000 0x3800 0x10 && " \
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"mmc read 0x80740000 0x3A00 0x10 && " \
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"esbc_validate 0x80700000 && " \
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"esbc_validate 0x80740000 ;" \
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"fsl_mc start mc 0x80000000 0x80100000\0" \
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"mcmemsize=0x70000000\0"
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#endif
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#undef CONFIG_EXTRA_ENV_SETTINGS
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"BOARD=ls1088ardb\0" \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"fdt_addr=0x64f00000\0" \
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"kernel_addr=0x1000000\0" \
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"kernel_addr_sd=0x8000\0" \
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"kernelhdr_addr_sd=0x4000\0" \
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"kernel_start=0x580100000\0" \
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"kernelheader_start=0x580800000\0" \
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"scriptaddr=0x80000000\0" \
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"scripthdraddr=0x80080000\0" \
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"fdtheader_addr_r=0x80100000\0" \
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"kernelheader_addr=0x800000\0" \
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"kernelheader_addr_r=0x80200000\0" \
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"kernel_addr_r=0x81000000\0" \
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"kernelheader_size=0x40000\0" \
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"fdt_addr_r=0x90000000\0" \
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"load_addr=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"kernel_size_sd=0x14000\0" \
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"kernelhdr_size_sd=0x10\0" \
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MC_INIT_CMD \
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BOOTENV \
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"boot_scripts=ls1088ardb_boot.scr\0" \
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"boot_script_hdr=hdr_ls1088ardb_bs.out\0" \
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"scan_dev_for_boot_part=" \
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"part list ${devtype} ${devnum} devplist; " \
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"env exists devplist || setenv devplist 1; " \
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"for distro_bootpart in ${devplist}; do " \
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"if fstype ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"bootfstype; then " \
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"run scan_dev_for_boot; " \
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"fi; " \
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"done\0" \
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"scan_dev_for_boot=" \
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"echo Scanning ${devtype} " \
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"${devnum}:${distro_bootpart}...; " \
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"for prefix in ${boot_prefixes}; do " \
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"run scan_dev_for_scripts; " \
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"done;\0" \
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"boot_a_script=" \
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"load ${devtype} ${devnum}:${distro_bootpart} " \
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"${scriptaddr} ${prefix}${script}; " \
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"env exists secureboot && load ${devtype} " \
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"${devnum}:${distro_bootpart} " \
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"${scripthdraddr} ${prefix}${boot_script_hdr} " \
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"&& esbc_validate ${scripthdraddr};" \
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"source ${scriptaddr}\0" \
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"installer=load mmc 0:2 $load_addr " \
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"/flex_installer_arm64.itb; " \
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"env exists mcinitcmd && run mcinitcmd && " \
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"mmc read 0x80200000 0x6800 0x800;" \
|
|
"fsl_mc apply dpl 0x80200000;" \
|
|
"bootm $load_addr#ls1088ardb\0" \
|
|
"qspi_bootcmd=echo Trying load from qspi..;" \
|
|
"sf probe && sf read $load_addr " \
|
|
"$kernel_addr $kernel_size ; env exists secureboot " \
|
|
"&& sf read $kernelheader_addr_r $kernelheader_addr " \
|
|
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
|
|
"bootm $load_addr#$BOARD\0" \
|
|
"sd_bootcmd=echo Trying load from sd card..;" \
|
|
"mmcinfo; mmc read $load_addr " \
|
|
"$kernel_addr_sd $kernel_size_sd ;" \
|
|
"env exists secureboot && mmc read $kernelheader_addr_r "\
|
|
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
|
|
" && esbc_validate ${kernelheader_addr_r};" \
|
|
"bootm $load_addr#$BOARD\0"
|
|
|
|
#undef CONFIG_BOOTCOMMAND
|
|
#if defined(CONFIG_QSPI_BOOT)
|
|
/* Try to boot an on-QSPI kernel first, then do normal distro boot */
|
|
#define CONFIG_BOOTCOMMAND \
|
|
"sf read 0x80200000 0xd00000 0x100000;" \
|
|
"env exists mcinitcmd && env exists secureboot " \
|
|
" && sf read 0x80780000 0x780000 0x100000 " \
|
|
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
|
|
"&& fsl_mc apply dpl 0x80200000;" \
|
|
"run distro_bootcmd;run qspi_bootcmd;" \
|
|
"env exists secureboot && esbc_halt;"
|
|
|
|
/* Try to boot an on-SD kernel first, then do normal distro boot */
|
|
#elif defined(CONFIG_SD_BOOT)
|
|
#define CONFIG_BOOTCOMMAND \
|
|
"env exists mcinitcmd && mmcinfo; " \
|
|
"mmc read 0x80200000 0x6800 0x800; " \
|
|
"env exists mcinitcmd && env exists secureboot " \
|
|
" && mmc read 0x80780000 0x3800 0x10 " \
|
|
"&& esbc_validate 0x80780000;env exists mcinitcmd " \
|
|
"&& fsl_mc apply dpl 0x80200000;" \
|
|
"run distro_bootcmd;run sd_bootcmd;" \
|
|
"env exists secureboot && esbc_halt;"
|
|
#endif
|
|
|
|
/* MAC/PHY configuration */
|
|
#ifdef CONFIG_FSL_MC_ENET
|
|
#define CONFIG_PHYLIB_10G
|
|
#define CONFIG_PHY_GIGE
|
|
#define CONFIG_PHYLIB
|
|
|
|
#define CONFIG_PHY_VITESSE
|
|
#define CONFIG_PHY_AQUANTIA
|
|
#define AQ_PHY_ADDR1 0x00
|
|
#define AQR105_IRQ_MASK 0x00000004
|
|
|
|
#define QSGMII1_PORT1_PHY_ADDR 0x0c
|
|
#define QSGMII1_PORT2_PHY_ADDR 0x0d
|
|
#define QSGMII1_PORT3_PHY_ADDR 0x0e
|
|
#define QSGMII1_PORT4_PHY_ADDR 0x0f
|
|
#define QSGMII2_PORT1_PHY_ADDR 0x1c
|
|
#define QSGMII2_PORT2_PHY_ADDR 0x1d
|
|
#define QSGMII2_PORT3_PHY_ADDR 0x1e
|
|
#define QSGMII2_PORT4_PHY_ADDR 0x1f
|
|
|
|
#define CONFIG_MII
|
|
#define CONFIG_ETHPRIME "DPMAC1@xgmii"
|
|
#define CONFIG_PHY_GIGE
|
|
#endif
|
|
#endif
|
|
|
|
/* MMC */
|
|
#ifdef CONFIG_MMC
|
|
#define CONFIG_FSL_ESDHC
|
|
#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
|
|
#endif
|
|
|
|
#ifndef SPL_NO_ENV
|
|
#undef CONFIG_CMDLINE_EDITING
|
|
#include <config_distro_defaults.h>
|
|
|
|
#define BOOT_TARGET_DEVICES(func) \
|
|
func(MMC, mmc, 0) \
|
|
func(SCSI, scsi, 0) \
|
|
func(DHCP, dhcp, na)
|
|
#include <config_distro_bootcmd.h>
|
|
#endif
|
|
|
|
#include <asm/fsl_secure_boot.h>
|
|
|
|
#endif /* __LS1088A_RDB_H */
|