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50aa1d99ed
Add support for the HS400 mode to SDHI driver. This uses the up-tune mechanism from already supported HS200 tuning. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
157 lines
6.9 KiB
C
157 lines
6.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Socionext Inc.
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* Author: Masahiro Yamada <yamada.masahiro@socionext.com>
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*/
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#ifndef __TMIO_COMMON_H__
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#define __TMIO_COMMON_H__
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#define TMIO_SD_CMD 0x000 /* command */
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#define TMIO_SD_CMD_NOSTOP BIT(14) /* No automatic CMD12 issue */
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#define TMIO_SD_CMD_MULTI BIT(13) /* multiple block transfer */
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#define TMIO_SD_CMD_RD BIT(12) /* 1: read, 0: write */
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#define TMIO_SD_CMD_DATA BIT(11) /* data transfer */
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#define TMIO_SD_CMD_APP BIT(6) /* ACMD preceded by CMD55 */
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#define TMIO_SD_CMD_NORMAL (0 << 8)/* auto-detect of resp-type */
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#define TMIO_SD_CMD_RSP_NONE (3 << 8)/* response: none */
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#define TMIO_SD_CMD_RSP_R1 (4 << 8)/* response: R1, R5, R6, R7 */
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#define TMIO_SD_CMD_RSP_R1B (5 << 8)/* response: R1b, R5b */
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#define TMIO_SD_CMD_RSP_R2 (6 << 8)/* response: R2 */
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#define TMIO_SD_CMD_RSP_R3 (7 << 8)/* response: R3, R4 */
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#define TMIO_SD_ARG 0x008 /* command argument */
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#define TMIO_SD_STOP 0x010 /* stop action control */
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#define TMIO_SD_STOP_SEC BIT(8) /* use sector count */
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#define TMIO_SD_STOP_STP BIT(0) /* issue CMD12 */
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#define TMIO_SD_SECCNT 0x014 /* sector counter */
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#define TMIO_SD_RSP10 0x018 /* response[39:8] */
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#define TMIO_SD_RSP32 0x020 /* response[71:40] */
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#define TMIO_SD_RSP54 0x028 /* response[103:72] */
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#define TMIO_SD_RSP76 0x030 /* response[127:104] */
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#define TMIO_SD_INFO1 0x038 /* IRQ status 1 */
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#define TMIO_SD_INFO1_CD BIT(5) /* state of card detect */
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#define TMIO_SD_INFO1_INSERT BIT(4) /* card inserted */
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#define TMIO_SD_INFO1_REMOVE BIT(3) /* card removed */
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#define TMIO_SD_INFO1_CMP BIT(2) /* data complete */
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#define TMIO_SD_INFO1_RSP BIT(0) /* response complete */
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#define TMIO_SD_INFO2 0x03c /* IRQ status 2 */
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#define TMIO_SD_INFO2_ERR_ILA BIT(15) /* illegal access err */
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#define TMIO_SD_INFO2_CBSY BIT(14) /* command busy */
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#define TMIO_SD_INFO2_SCLKDIVEN BIT(13) /* command setting reg ena */
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#define TMIO_SD_INFO2_BWE BIT(9) /* write buffer ready */
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#define TMIO_SD_INFO2_BRE BIT(8) /* read buffer ready */
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#define TMIO_SD_INFO2_DAT0 BIT(7) /* SDDAT0 */
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#define TMIO_SD_INFO2_ERR_RTO BIT(6) /* response time out */
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#define TMIO_SD_INFO2_ERR_ILR BIT(5) /* illegal read err */
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#define TMIO_SD_INFO2_ERR_ILW BIT(4) /* illegal write err */
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#define TMIO_SD_INFO2_ERR_TO BIT(3) /* time out error */
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#define TMIO_SD_INFO2_ERR_END BIT(2) /* END bit error */
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#define TMIO_SD_INFO2_ERR_CRC BIT(1) /* CRC error */
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#define TMIO_SD_INFO2_ERR_IDX BIT(0) /* cmd index error */
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#define TMIO_SD_INFO1_MASK 0x040
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#define TMIO_SD_INFO2_MASK 0x044
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#define TMIO_SD_CLKCTL 0x048 /* clock divisor */
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#define TMIO_SD_CLKCTL_DIV_MASK 0x104ff
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#define TMIO_SD_CLKCTL_DIV1024 BIT(16) /* SDCLK = CLK / 1024 */
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#define TMIO_SD_CLKCTL_DIV512 BIT(7) /* SDCLK = CLK / 512 */
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#define TMIO_SD_CLKCTL_DIV256 BIT(6) /* SDCLK = CLK / 256 */
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#define TMIO_SD_CLKCTL_DIV128 BIT(5) /* SDCLK = CLK / 128 */
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#define TMIO_SD_CLKCTL_DIV64 BIT(4) /* SDCLK = CLK / 64 */
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#define TMIO_SD_CLKCTL_DIV32 BIT(3) /* SDCLK = CLK / 32 */
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#define TMIO_SD_CLKCTL_DIV16 BIT(2) /* SDCLK = CLK / 16 */
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#define TMIO_SD_CLKCTL_DIV8 BIT(1) /* SDCLK = CLK / 8 */
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#define TMIO_SD_CLKCTL_DIV4 BIT(0) /* SDCLK = CLK / 4 */
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#define TMIO_SD_CLKCTL_DIV2 0 /* SDCLK = CLK / 2 */
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#define TMIO_SD_CLKCTL_DIV1 BIT(10) /* SDCLK = CLK */
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#define TMIO_SD_CLKCTL_RCAR_DIV1 0xff /* SDCLK = CLK (RCar ver.) */
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#define TMIO_SD_CLKCTL_OFFEN BIT(9) /* stop SDCLK when unused */
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#define TMIO_SD_CLKCTL_SCLKEN BIT(8) /* SDCLK output enable */
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#define TMIO_SD_SIZE 0x04c /* block size */
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#define TMIO_SD_OPTION 0x050
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#define TMIO_SD_OPTION_WIDTH_MASK (5 << 13)
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#define TMIO_SD_OPTION_WIDTH_1 (4 << 13)
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#define TMIO_SD_OPTION_WIDTH_4 (0 << 13)
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#define TMIO_SD_OPTION_WIDTH_8 (1 << 13)
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#define TMIO_SD_BUF 0x060 /* read/write buffer */
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#define TMIO_SD_EXTMODE 0x1b0
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#define TMIO_SD_EXTMODE_DMA_EN BIT(1) /* transfer 1: DMA, 0: pio */
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#define TMIO_SD_SOFT_RST 0x1c0
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#define TMIO_SD_SOFT_RST_RSTX BIT(0) /* reset deassert */
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#define TMIO_SD_VERSION 0x1c4 /* version register */
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#define TMIO_SD_VERSION_IP 0xff /* IP version */
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#define TMIO_SD_HOST_MODE 0x1c8
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#define TMIO_SD_IF_MODE 0x1cc
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#define TMIO_SD_IF_MODE_DDR BIT(0) /* DDR mode */
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#define TMIO_SD_VOLT 0x1e4 /* voltage switch */
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#define TMIO_SD_VOLT_MASK (3 << 0)
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#define TMIO_SD_VOLT_OFF (0 << 0)
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#define TMIO_SD_VOLT_330 (1 << 0)/* 3.3V signal */
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#define TMIO_SD_VOLT_180 (2 << 0)/* 1.8V signal */
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#define TMIO_SD_DMA_MODE 0x410
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#define TMIO_SD_DMA_MODE_DIR_RD BIT(16) /* 1: from device, 0: to dev */
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#define TMIO_SD_DMA_MODE_ADDR_INC BIT(0) /* 1: address inc, 0: fixed */
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#define TMIO_SD_DMA_CTL 0x414
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#define TMIO_SD_DMA_CTL_START BIT(0) /* start DMA (auto cleared) */
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#define TMIO_SD_DMA_RST 0x418
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#define TMIO_SD_DMA_RST_RD BIT(9)
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#define TMIO_SD_DMA_RST_WR BIT(8)
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#define TMIO_SD_DMA_INFO1 0x420
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#define TMIO_SD_DMA_INFO1_END_RD2 BIT(20) /* DMA from device is complete (uniphier) */
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#define TMIO_SD_DMA_INFO1_END_RD BIT(17) /* DMA from device is complete (renesas) */
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#define TMIO_SD_DMA_INFO1_END_WR BIT(16) /* DMA to device is complete */
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#define TMIO_SD_DMA_INFO1_MASK 0x424
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#define TMIO_SD_DMA_INFO2 0x428
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#define TMIO_SD_DMA_INFO2_ERR_RD BIT(17)
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#define TMIO_SD_DMA_INFO2_ERR_WR BIT(16)
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#define TMIO_SD_DMA_INFO2_MASK 0x42c
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#define TMIO_SD_DMA_ADDR_L 0x440
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#define TMIO_SD_DMA_ADDR_H 0x444
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/* alignment required by the DMA engine of this controller */
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#define TMIO_SD_DMA_MINALIGN 0x10
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struct tmio_sd_plat {
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struct mmc_config cfg;
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struct mmc mmc;
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};
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struct tmio_sd_priv {
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void __iomem *regbase;
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unsigned int version;
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u32 caps;
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#define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
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#define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
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#define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */
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#define TMIO_SD_CAP_64BIT BIT(3) /* Controller is 64bit */
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#define TMIO_SD_CAP_16BIT BIT(4) /* Controller is 16bit */
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#define TMIO_SD_CAP_RCAR_GEN2 BIT(5) /* Renesas RCar version of IP */
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#define TMIO_SD_CAP_RCAR_GEN3 BIT(6) /* Renesas RCar version of IP */
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#define TMIO_SD_CAP_RCAR_UHS BIT(7) /* Renesas RCar UHS/SDR modes */
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#define TMIO_SD_CAP_RCAR \
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(TMIO_SD_CAP_RCAR_GEN2 | TMIO_SD_CAP_RCAR_GEN3)
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#ifdef CONFIG_DM_REGULATOR
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struct udevice *vqmmc_dev;
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#endif
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#if CONFIG_IS_ENABLED(CLK)
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struct clk clk;
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#endif
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#if CONFIG_IS_ENABLED(RENESAS_SDHI)
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u8 tap_set;
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u8 nrtaps;
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#endif
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ulong (*clk_get_rate)(struct tmio_sd_priv *);
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};
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int tmio_sd_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
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struct mmc_data *data);
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int tmio_sd_set_ios(struct udevice *dev);
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int tmio_sd_get_cd(struct udevice *dev);
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int tmio_sd_bind(struct udevice *dev);
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int tmio_sd_probe(struct udevice *dev, u32 quirks);
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u32 tmio_sd_readl(struct tmio_sd_priv *priv, unsigned int reg);
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void tmio_sd_writel(struct tmio_sd_priv *priv,
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u32 val, unsigned int reg);
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#endif /* __TMIO_COMMON_H__ */
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