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bf7bd4e725
Phy mode is a board property and it can be different between multiple board and ports, so it should not be hardcoded in driver to one specific mode. So adding a field in eth_priv_t structure to pass phy mode to driver. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
126 lines
2.5 KiB
C
126 lines
2.5 KiB
C
/*
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* K2L EVM : Board initialization
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/ddr3.h>
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#include <asm/arch/hardware.h>
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#include <asm/ti-common/keystone_net.h>
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DECLARE_GLOBAL_DATA_PTR;
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unsigned int external_clk[ext_clk_count] = {
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[sys_clk] = 122880000,
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[alt_core_clk] = 100000000,
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[pa_clk] = 122880000,
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[tetris_clk] = 122880000,
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[ddr3a_clk] = 100000000,
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};
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static struct pll_init_data core_pll_config[NUM_SPDS] = {
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[SPD800] = CORE_PLL_799,
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[SPD1000] = CORE_PLL_1000,
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[SPD1200] = CORE_PLL_1198,
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};
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s16 divn_val[16] = {
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0, 0, 1, 4, 23, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
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};
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static struct pll_init_data tetris_pll_config[] = {
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[SPD800] = TETRIS_PLL_799,
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[SPD1000] = TETRIS_PLL_1000,
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[SPD1200] = TETRIS_PLL_1198,
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[SPD1350] = TETRIS_PLL_1352,
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[SPD1400] = TETRIS_PLL_1401,
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};
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static struct pll_init_data pa_pll_config =
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PASS_PLL_983;
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struct pll_init_data *get_pll_init_data(int pll)
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{
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int speed;
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struct pll_init_data *data;
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switch (pll) {
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case MAIN_PLL:
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speed = get_max_dev_speed();
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data = &core_pll_config[speed];
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break;
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case TETRIS_PLL:
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speed = get_max_arm_speed();
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data = &tetris_pll_config[speed];
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break;
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case PASS_PLL:
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data = &pa_pll_config;
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break;
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default:
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data = NULL;
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}
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return data;
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}
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#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET
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struct eth_priv_t eth_priv_cfg[] = {
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{
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.int_name = "K2L_EMAC",
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.rx_flow = 0,
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.phy_addr = 0,
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.slave_port = 1,
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.sgmii_link_type = SGMII_LINK_MAC_PHY,
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.phy_if = PHY_INTERFACE_MODE_SGMII,
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},
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{
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.int_name = "K2L_EMAC1",
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.rx_flow = 8,
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.phy_addr = 1,
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.slave_port = 2,
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.sgmii_link_type = SGMII_LINK_MAC_PHY,
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.phy_if = PHY_INTERFACE_MODE_SGMII,
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},
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{
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.int_name = "K2L_EMAC2",
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.rx_flow = 16,
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.phy_addr = 2,
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.slave_port = 3,
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.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
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.phy_if = PHY_INTERFACE_MODE_SGMII,
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},
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{
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.int_name = "K2L_EMAC3",
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.rx_flow = 32,
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.phy_addr = 3,
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.slave_port = 4,
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.sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED,
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.phy_if = PHY_INTERFACE_MODE_SGMII,
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},
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};
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int get_num_eth_ports(void)
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{
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return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t);
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}
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#endif
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#ifdef CONFIG_BOARD_EARLY_INIT_F
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int board_early_init_f(void)
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{
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init_plls();
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return 0;
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}
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#endif
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#ifdef CONFIG_SPL_BUILD
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void spl_init_keystone_plls(void)
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{
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init_plls();
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}
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#endif
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