mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-18 01:03:05 +00:00
2ef53647d1
The USB support is not by default enabled on all designs, so it does not make seance to have USB specific erratum's enabled on such a designs. On our internal Hitachi-Powergrids design not using the USB controller there is a crash when accessing those specific memory locations selected by the erratum flags. Signed-off-by: Aleksandar Gerasimovski <aleksandar.gerasimovski@hitachi-powergrids.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
104 lines
2.3 KiB
Text
104 lines
2.3 KiB
Text
config ARCH_LS1021A
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bool
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select SYS_FSL_DDR_BE if SYS_FSL_DDR
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select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
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select SYS_FSL_ERRATUM_A008378
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select SYS_FSL_ERRATUM_A008407
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select SYS_FSL_ERRATUM_A008850
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select SYS_FSL_ERRATUM_A008997 if USB
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select SYS_FSL_ERRATUM_A009007 if USB
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select SYS_FSL_ERRATUM_A009008 if USB
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select SYS_FSL_ERRATUM_A009663
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select SYS_FSL_ERRATUM_A009798 if USB
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select SYS_FSL_ERRATUM_A009942
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select SYS_FSL_ERRATUM_A010315
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select SYS_FSL_HAS_CCI400
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select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
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select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
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select SYS_FSL_HAS_SEC
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select SYS_FSL_SEC_COMPAT_5
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select SYS_FSL_SEC_LE
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select SYS_FSL_SRDS_1
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select SYS_HAS_SERDES
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imply CMD_PCI
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imply SCSI
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imply SCSI_AHCI
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menu "LS102xA architecture"
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depends on ARCH_LS1021A
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config LS1_DEEP_SLEEP
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bool "Deep sleep"
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config MAX_CPUS
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int "Maximum number of CPUs permitted for LS102xA"
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default 2
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help
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Set this number to the maximum number of possible CPUs in the SoC.
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SoCs may have multiple clusters with each cluster may have multiple
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ports. If some ports are reserved but higher ports are used for
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cores, count the reserved ports. This will allocate enough memory
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in spin table to properly handle all cores.
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config NXP_ESBC
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bool "NXP_ESBC"
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help
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Enable Freescale Secure Boot feature. Normally selected
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by defconfig. If unsure, do not change.
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config SYS_CCI400_OFFSET
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hex "Offset for CCI400 base"
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depends on SYS_FSL_HAS_CCI400
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default 0x180000
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help
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Offset for CCI400 base.
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CCI400 base addr = CCSRBAR + CCI400_OFFSET
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config SYS_FSL_ERRATUM_A008850
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bool
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help
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Workaround for DDR erratum A008850
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config SYS_FSL_ERRATUM_A008997
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bool
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help
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Workaround for USB PHY erratum A008997
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config SYS_FSL_ERRATUM_A009007
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bool
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help
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Workaround for USB PHY erratum A009007
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config SYS_FSL_ERRATUM_A009008
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bool
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help
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Workaround for USB PHY erratum A009008
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config SYS_FSL_ERRATUM_A009798
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bool
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help
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Workaround for USB PHY erratum A009798
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config SYS_FSL_ERRATUM_A010315
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bool "Workaround for PCIe erratum A010315"
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config SYS_FSL_HAS_CCI400
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bool
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config SYS_FSL_SRDS_1
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bool
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config SYS_FSL_SRDS_2
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bool
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config SYS_HAS_SERDES
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bool
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config SYS_FSL_IFC_BANK_COUNT
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int "Maximum banks of Integrated flash controller"
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default 8
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config SYS_FSL_ERRATUM_A008407
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bool
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endmenu
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