mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-19 11:18:28 +00:00
200 lines
4.8 KiB
ArmAsm
200 lines
4.8 KiB
ArmAsm
/*
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* Memory Setup stuff - taken from blob memsetup.S
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*
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* Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
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* Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
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*
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* Modified for the at91rm9200dk board by
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* (C) Copyright 2004
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* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#ifdef CONFIG_BOOTBINFUNC
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/*
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* some parameters for the board
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*
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* This is based on rm9200dk.cfg for the BDI2000 from ABATRON which in
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* turn is based on the boot.bin code from ATMEL
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*
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*/
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/* flash */
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#define MC_PUIA 0xFFFFFF10
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#define MC_PUIA_VAL 0x00000000
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#define MC_PUP 0xFFFFFF50
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#define MC_PUP_VAL 0x00000000
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#define MC_PUER 0xFFFFFF54
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#define MC_PUER_VAL 0x00000000
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#define MC_ASR 0xFFFFFF04
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#define MC_ASR_VAL 0x00000000
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#define MC_AASR 0xFFFFFF08
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#define MC_AASR_VAL 0x00000000
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#define EBI_CFGR 0xFFFFFF64
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#define EBI_CFGR_VAL 0x00000000
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#define SMC2_CSR 0xFFFFFF70
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#define SMC2_CSR_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
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/* clocks */
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#define PLLAR 0xFFFFFC28
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#define PLLAR_VAL 0x20263E04 /* 179.712000 MHz for PCK */
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#define PLLBR 0xFFFFFC2C
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#define PLLBR_VAL 0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
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#define MCKR 0xFFFFFC30
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/* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
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#define MCKR_VAL 0x00000202
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/* sdram */
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#define PIOC_ASR 0xFFFFF870
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#define PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as Perip (D16/D31) */
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#define PIOC_BSR 0xFFFFF874
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#define PIOC_BSR_VAL 0x00000000
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#define PIOC_PDR 0xFFFFF804
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#define PIOC_PDR_VAL 0xFFFF0000
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#define EBI_CSA 0xFFFFFF60
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#define EBI_CSA_VAL 0x00000002 /* CS1=SDRAM */
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#define SDRC_CR 0xFFFFFF98
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#define SDRC_CR_VAL 0x2188c155 /* set up the SDRAM */
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#define SDRAM 0x20000000 /* address of the SDRAM */
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#define SDRAM1 0x20000080 /* address of the SDRAM */
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#define SDRAM_VAL 0x00000000 /* value written to SDRAM */
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#define SDRC_MR 0xFFFFFF90
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#define SDRC_MR_VAL 0x00000002 /* Precharge All */
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#define SDRC_MR_VAL1 0x00000004 /* refresh */
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#define SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
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#define SDRC_MR_VAL3 0x00000000 /* Normal Mode */
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#define SDRC_TR 0xFFFFFF94
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#define SDRC_TR_VAL 0x000002E0 /* Write refresh rate */
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_TEXT_BASE:
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.word TEXT_BASE
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.globl lowlevelinit
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lowlevelinit:
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/* memory control configuration */
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/* this isn't very elegant, but what the heck */
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ldr r0, =SMRDATA
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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add r2, r0, #80
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0:
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/* the address */
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ldr r1, [r0], #4
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/* the value */
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ldr r3, [r0], #4
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str r3, [r1]
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cmp r2, r0
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bne 0b
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/* delay - this is all done by guess */
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ldr r0, =0x00010000
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1:
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subs r0, r0, #1
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bhi 1b
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ldr r0, =SMRDATA1
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ldr r1, _TEXT_BASE
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sub r0, r0, r1
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add r2, r0, #176
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2:
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/* the address */
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ldr r1, [r0], #4
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/* the value */
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ldr r3, [r0], #4
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str r3, [r1]
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cmp r2, r0
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bne 2b
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/* everything is fine now */
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mov pc, lr
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.ltorg
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SMRDATA:
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.word MC_PUIA
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.word MC_PUIA_VAL
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.word MC_PUP
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.word MC_PUP_VAL
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.word MC_PUER
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.word MC_PUER_VAL
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.word MC_ASR
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.word MC_ASR_VAL
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.word MC_AASR
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.word MC_AASR_VAL
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.word EBI_CFGR
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.word EBI_CFGR_VAL
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.word SMC2_CSR
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.word SMC2_CSR_VAL
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.word PLLAR
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.word PLLAR_VAL
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.word PLLBR
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.word PLLBR_VAL
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.word MCKR
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.word MCKR_VAL
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/* SMRDATA is 80 bytes long */
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/* here there's a delay of 100 */
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SMRDATA1:
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.word PIOC_ASR
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.word PIOC_ASR_VAL
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.word PIOC_BSR
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.word PIOC_BSR_VAL
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.word PIOC_PDR
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.word PIOC_PDR_VAL
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.word EBI_CSA
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.word EBI_CSA_VAL
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.word SDRC_CR
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.word SDRC_CR_VAL
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.word SDRC_MR
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.word SDRC_MR_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRC_MR
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.word SDRC_MR_VAL1
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRC_MR
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.word SDRC_MR_VAL2
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.word SDRAM1
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.word SDRAM_VAL
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.word SDRC_TR
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.word SDRC_TR_VAL
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.word SDRAM
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.word SDRAM_VAL
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.word SDRC_MR
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.word SDRC_MR_VAL3
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.word SDRAM
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.word SDRAM_VAL
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/* SMRDATA1 is 176 bytes long */
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#endif /* CONFIG_BOOTBINFUNC */
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