mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-18 02:38:56 +00:00
8cb4817d0f
Rather than probing the cache line sizes on every call of any cache maintenance function, probe them once during boot & store the values in the global data structure for later use. This will reduce the overhead of the cache maintenance functions, which isn't a big deal yet but becomes more important once L2 caches which may expose their properties via coprocessor 2 or the CM are supported. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
44 lines
778 B
C
44 lines
778 B
C
/*
|
|
* (C) Copyright 2003
|
|
* Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0+
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <command.h>
|
|
#include <linux/compiler.h>
|
|
#include <asm/cache.h>
|
|
#include <asm/mipsregs.h>
|
|
#include <asm/reboot.h>
|
|
|
|
void __weak _machine_restart(void)
|
|
{
|
|
fprintf(stderr, "*** reset failed ***\n");
|
|
|
|
while (1)
|
|
/* NOP */;
|
|
}
|
|
|
|
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
|
|
{
|
|
_machine_restart();
|
|
|
|
return 0;
|
|
}
|
|
|
|
void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1)
|
|
{
|
|
write_c0_entrylo0(low0);
|
|
write_c0_pagemask(pagemask);
|
|
write_c0_entrylo1(low1);
|
|
write_c0_entryhi(hi);
|
|
write_c0_index(index);
|
|
tlb_write_indexed();
|
|
}
|
|
|
|
int arch_cpu_init(void)
|
|
{
|
|
mips_cache_probe();
|
|
return 0;
|
|
}
|