mirror of
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8a8d24bdf1
Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
620 lines
19 KiB
C
620 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2013-2018 Hannes Schmelzer <oe5hpm@oevsv.at>
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* B&R Industrial Automation GmbH - http://www.br-automation.com
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* Copyright (C) 2020 Dario Binacchi <dariobin@libero.it>
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*
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* minimal framebuffer driver for TI's AM335x SoC to be compatible with
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* Wolfgang Denk's LCD-Framework (CONFIG_LCD, common/lcd.c)
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*
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* - supporting 16/24/32bit RGB/TFT raster Mode (not using palette)
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* - sets up LCD controller as in 'am335x_lcdpanel' struct given
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* - starts output DMA from gd->fb_base buffer
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*/
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#include <common.h>
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#include <dm.h>
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#include <lcd.h>
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#include <log.h>
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#include <video.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/utils.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include "am335x-fb.h"
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#define LCDC_FMAX 200000000
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/* LCD Control Register */
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#define LCDC_CTRL_CLK_DIVISOR_MASK GENMASK(15, 8)
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#define LCDC_CTRL_RASTER_MODE BIT(0)
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#define LCDC_CTRL_CLK_DIVISOR(x) (((x) & GENMASK(7, 0)) << 8)
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/* LCD Clock Enable Register */
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#define LCDC_CLKC_ENABLE_CORECLKEN BIT(0)
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#define LCDC_CLKC_ENABLE_LIDDCLKEN BIT(1)
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#define LCDC_CLKC_ENABLE_DMACLKEN BIT(2)
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/* LCD DMA Control Register */
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#define LCDC_DMA_CTRL_BURST_SIZE(x) (((x) & GENMASK(2, 0)) << 4)
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#define LCDC_DMA_CTRL_BURST_1 0x0
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#define LCDC_DMA_CTRL_BURST_2 0x1
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#define LCDC_DMA_CTRL_BURST_4 0x2
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#define LCDC_DMA_CTRL_BURST_8 0x3
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#define LCDC_DMA_CTRL_BURST_16 0x4
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#define LCDC_DMA_CTRL_FIFO_TH(x) (((x) & GENMASK(2, 0)) << 8)
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/* LCD Timing_0 Register */
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#define LCDC_RASTER_TIMING_0_HORMSB(x) ((((x) - 1) & BIT(10)) >> 7)
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#define LCDC_RASTER_TIMING_0_HORLSB(x) (((((x) >> 4) - 1) & GENMASK(5, 0)) << 4)
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#define LCDC_RASTER_TIMING_0_HSWLSB(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
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#define LCDC_RASTER_TIMING_0_HFPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 16)
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#define LCDC_RASTER_TIMING_0_HBPLSB(x) ((((x) - 1) & GENMASK(7, 0)) << 24)
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/* LCD Timing_1 Register */
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#define LCDC_RASTER_TIMING_1_VERLSB(x) (((x) - 1) & GENMASK(9, 0))
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#define LCDC_RASTER_TIMING_1_VSW(x) ((((x) - 1) & GENMASK(5, 0)) << 10)
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#define LCDC_RASTER_TIMING_1_VFP(x) (((x) & GENMASK(7, 0)) << 16)
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#define LCDC_RASTER_TIMING_1_VBP(x) (((x) & GENMASK(7, 0)) << 24)
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/* LCD Timing_2 Register */
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#define LCDC_RASTER_TIMING_2_HFPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 8)
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#define LCDC_RASTER_TIMING_2_HBPMSB(x) ((((x) - 1) & GENMASK(9, 8)) >> 4)
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#define LCDC_RASTER_TIMING_2_ACB(x) (((x) & GENMASK(7, 0)) << 8)
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#define LCDC_RASTER_TIMING_2_ACBI(x) (((x) & GENMASK(3, 0)) << 16)
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#define LCDC_RASTER_TIMING_2_VSYNC_INVERT BIT(20)
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#define LCDC_RASTER_TIMING_2_HSYNC_INVERT BIT(21)
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#define LCDC_RASTER_TIMING_2_PXCLK_INVERT BIT(22)
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#define LCDC_RASTER_TIMING_2_DE_INVERT BIT(23)
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#define LCDC_RASTER_TIMING_2_HSVS_RISEFALL BIT(24)
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#define LCDC_RASTER_TIMING_2_HSVS_CONTROL BIT(25)
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#define LCDC_RASTER_TIMING_2_VERMSB(x) ((((x) - 1) & BIT(10)) << 16)
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#define LCDC_RASTER_TIMING_2_HSWMSB(x) ((((x) - 1) & GENMASK(9, 6)) << 21)
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/* LCD Raster Ctrl Register */
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#define LCDC_RASTER_CTRL_ENABLE BIT(0)
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#define LCDC_RASTER_CTRL_TFT_MODE BIT(7)
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#define LCDC_RASTER_CTRL_DATA_ORDER BIT(8)
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#define LCDC_RASTER_CTRL_REQDLY(x) (((x) & GENMASK(7, 0)) << 12)
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#define LCDC_RASTER_CTRL_PALMODE_RAWDATA (0x02 << 20)
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#define LCDC_RASTER_CTRL_TFT_ALT_ENABLE BIT(23)
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#define LCDC_RASTER_CTRL_TFT_24BPP_MODE BIT(25)
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#define LCDC_RASTER_CTRL_TFT_24BPP_UNPACK BIT(26)
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struct am335x_lcdhw {
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unsigned int pid; /* 0x00 */
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unsigned int ctrl; /* 0x04 */
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unsigned int gap0; /* 0x08 */
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unsigned int lidd_ctrl; /* 0x0C */
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unsigned int lidd_cs0_conf; /* 0x10 */
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unsigned int lidd_cs0_addr; /* 0x14 */
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unsigned int lidd_cs0_data; /* 0x18 */
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unsigned int lidd_cs1_conf; /* 0x1C */
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unsigned int lidd_cs1_addr; /* 0x20 */
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unsigned int lidd_cs1_data; /* 0x24 */
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unsigned int raster_ctrl; /* 0x28 */
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unsigned int raster_timing0; /* 0x2C */
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unsigned int raster_timing1; /* 0x30 */
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unsigned int raster_timing2; /* 0x34 */
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unsigned int raster_subpanel; /* 0x38 */
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unsigned int raster_subpanel2; /* 0x3C */
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unsigned int lcddma_ctrl; /* 0x40 */
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unsigned int lcddma_fb0_base; /* 0x44 */
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unsigned int lcddma_fb0_ceiling; /* 0x48 */
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unsigned int lcddma_fb1_base; /* 0x4C */
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unsigned int lcddma_fb1_ceiling; /* 0x50 */
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unsigned int sysconfig; /* 0x54 */
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unsigned int irqstatus_raw; /* 0x58 */
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unsigned int irqstatus; /* 0x5C */
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unsigned int irqenable_set; /* 0x60 */
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unsigned int irqenable_clear; /* 0x64 */
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unsigned int gap1; /* 0x68 */
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unsigned int clkc_enable; /* 0x6C */
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unsigned int clkc_reset; /* 0x70 */
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};
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struct dpll_data {
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unsigned long rounded_rate;
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u16 rounded_m;
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u8 rounded_n;
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u8 rounded_div;
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};
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DECLARE_GLOBAL_DATA_PTR;
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/**
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* am335x_dpll_round_rate() - Round a target rate for an OMAP DPLL
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*
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* @dpll_data: struct dpll_data pointer for the DPLL
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* @rate: New DPLL clock rate
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* @return rounded rate and the computed m, n and div values in the dpll_data
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* structure, or -ve error code.
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*/
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static ulong am335x_dpll_round_rate(struct dpll_data *dd, ulong rate)
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{
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unsigned int m, n, d;
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unsigned long rounded_rate;
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int err, err_r;
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dd->rounded_rate = -EFAULT;
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err = rate;
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err_r = err;
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for (d = 2; err && d < 255; d++) {
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for (m = 2; m < 2047; m++) {
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if ((V_OSCK * m) < (rate * d))
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continue;
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n = (V_OSCK * m) / (rate * d);
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if (n > 127)
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break;
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if (((V_OSCK * m) / n) > LCDC_FMAX)
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break;
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rounded_rate = (V_OSCK * m) / n / d;
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err = abs(rounded_rate - rate);
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if (err < err_r) {
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err_r = err;
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dd->rounded_rate = rounded_rate;
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dd->rounded_m = m;
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dd->rounded_n = n;
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dd->rounded_div = d;
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if (err == 0)
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break;
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}
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}
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}
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debug("DPLL display: best error %d Hz (M %d, N %d, DIV %d)\n",
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err_r, dd->rounded_m, dd->rounded_n, dd->rounded_div);
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return dd->rounded_rate;
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}
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/**
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* am335x_fb_set_pixel_clk_rate() - Set pixel clock rate.
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*
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* @am335x_lcdhw: Base address of the LCD controller registers.
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* @rate: New clock rate in Hz.
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* @return new rate, or -ve error code.
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*/
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static ulong am335x_fb_set_pixel_clk_rate(struct am335x_lcdhw *regs, ulong rate)
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{
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struct dpll_params dpll_disp = { 1, 0, 1, -1, -1, -1, -1 };
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struct dpll_data dd;
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ulong round_rate;
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u32 reg;
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round_rate = am335x_dpll_round_rate(&dd, rate);
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if (IS_ERR_VALUE(round_rate))
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return round_rate;
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dpll_disp.m = dd.rounded_m;
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dpll_disp.n = dd.rounded_n;
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do_setup_dpll(&dpll_disp_regs, &dpll_disp);
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reg = readl(®s->ctrl) & ~LCDC_CTRL_CLK_DIVISOR_MASK;
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reg |= LCDC_CTRL_CLK_DIVISOR(dd.rounded_div);
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writel(reg, ®s->ctrl);
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return round_rate;
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}
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#if !CONFIG_IS_ENABLED(DM_VIDEO)
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#if !defined(LCD_CNTL_BASE)
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#error "hw-base address of LCD-Controller (LCD_CNTL_BASE) not defined!"
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#endif
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/* Macro definitions */
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#define FBSIZE(x) (((x)->hactive * (x)->vactive * (x)->bpp) >> 3)
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#define LCDC_RASTER_TIMING_2_INVMASK(x) ((x) & GENMASK(25, 20))
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static struct am335x_lcdhw *lcdhw = (void *)LCD_CNTL_BASE;
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int lcd_get_size(int *line_length)
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{
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*line_length = (panel_info.vl_col * NBITS(panel_info.vl_bpix)) / 8;
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return *line_length * panel_info.vl_row + 0x20;
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}
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int am335xfb_init(struct am335x_lcdpanel *panel)
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{
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u32 raster_ctrl = 0;
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struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
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ulong rate;
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u32 reg;
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if (gd->fb_base == 0) {
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printf("ERROR: no valid fb_base stored in GLOBAL_DATA_PTR!\n");
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return -1;
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}
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if (panel == NULL) {
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printf("ERROR: missing ptr to am335x_lcdpanel!\n");
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return -1;
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}
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/* We can already set the bits for the raster_ctrl in this check */
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switch (panel->bpp) {
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case 16:
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break;
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case 32:
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raster_ctrl |= LCDC_RASTER_CTRL_TFT_24BPP_UNPACK;
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/* fallthrough */
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case 24:
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raster_ctrl |= LCDC_RASTER_CTRL_TFT_24BPP_MODE;
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break;
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default:
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pr_err("am335x-fb: invalid bpp value: %d\n", panel->bpp);
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return -1;
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}
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/* check given clock-frequency */
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if (panel->pxl_clk > (LCDC_FMAX / 2)) {
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pr_err("am335x-fb: requested pxl-clk: %d not supported!\n",
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panel->pxl_clk);
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return -1;
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}
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debug("setting up LCD-Controller for %dx%dx%d (hfp=%d,hbp=%d,hsw=%d / ",
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panel->hactive, panel->vactive, panel->bpp,
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panel->hfp, panel->hbp, panel->hsw);
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debug("vfp=%d,vbp=%d,vsw=%d / clk=%d)\n",
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panel->vfp, panel->vfp, panel->vsw, panel->pxl_clk);
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debug("using frambuffer at 0x%08x with size %d.\n",
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(unsigned int)gd->fb_base, FBSIZE(panel));
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rate = am335x_fb_set_pixel_clk_rate(lcdhw, panel->pxl_clk);
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if (IS_ERR_VALUE(rate))
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return rate;
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/* clock source for LCDC from dispPLL M2 */
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writel(0x0, &cmdpll->clklcdcpixelclk);
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/* palette default entry */
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memset((void *)gd->fb_base, 0, 0x20);
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*(unsigned int *)gd->fb_base = 0x4000;
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/* point fb behind palette */
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gd->fb_base += 0x20;
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/* turn ON display through powercontrol function if accessible */
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if (panel->panel_power_ctrl != NULL)
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panel->panel_power_ctrl(1);
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debug("am335x-fb: wait for stable power ...\n");
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mdelay(panel->pup_delay);
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lcdhw->clkc_enable = LCDC_CLKC_ENABLE_CORECLKEN |
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LCDC_CLKC_ENABLE_LIDDCLKEN | LCDC_CLKC_ENABLE_DMACLKEN;
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lcdhw->raster_ctrl = 0;
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reg = lcdhw->ctrl & LCDC_CTRL_CLK_DIVISOR_MASK;
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reg |= LCDC_CTRL_RASTER_MODE;
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lcdhw->ctrl = reg;
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lcdhw->lcddma_fb0_base = gd->fb_base;
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lcdhw->lcddma_fb0_ceiling = gd->fb_base + FBSIZE(panel);
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lcdhw->lcddma_fb1_base = gd->fb_base;
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lcdhw->lcddma_fb1_ceiling = gd->fb_base + FBSIZE(panel);
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lcdhw->lcddma_ctrl = LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_16);
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lcdhw->raster_timing0 = LCDC_RASTER_TIMING_0_HORLSB(panel->hactive) |
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LCDC_RASTER_TIMING_0_HORMSB(panel->hactive) |
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LCDC_RASTER_TIMING_0_HFPLSB(panel->hfp) |
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LCDC_RASTER_TIMING_0_HBPLSB(panel->hbp) |
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LCDC_RASTER_TIMING_0_HSWLSB(panel->hsw);
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lcdhw->raster_timing1 = LCDC_RASTER_TIMING_1_VBP(panel->vbp) |
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LCDC_RASTER_TIMING_1_VFP(panel->vfp) |
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LCDC_RASTER_TIMING_1_VSW(panel->vsw) |
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LCDC_RASTER_TIMING_1_VERLSB(panel->vactive);
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lcdhw->raster_timing2 = LCDC_RASTER_TIMING_2_HSWMSB(panel->hsw) |
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LCDC_RASTER_TIMING_2_VERMSB(panel->vactive) |
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LCDC_RASTER_TIMING_2_INVMASK(panel->pol) |
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LCDC_RASTER_TIMING_2_HBPMSB(panel->hbp) |
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LCDC_RASTER_TIMING_2_HFPMSB(panel->hfp) |
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0x0000FF00; /* clk cycles for ac-bias */
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lcdhw->raster_ctrl = raster_ctrl |
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LCDC_RASTER_CTRL_PALMODE_RAWDATA |
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LCDC_RASTER_CTRL_TFT_MODE |
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LCDC_RASTER_CTRL_ENABLE;
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debug("am335x-fb: waiting picture to be stable.\n.");
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mdelay(panel->pon_delay);
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return 0;
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}
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#else /* CONFIG_DM_VIDEO */
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#define FBSIZE(t, p) (((t)->hactive.typ * (t)->vactive.typ * (p)->bpp) >> 3)
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enum {
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LCD_MAX_WIDTH = 2048,
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LCD_MAX_HEIGHT = 2048,
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LCD_MAX_LOG2_BPP = VIDEO_BPP32,
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};
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/**
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* tilcdc_panel_info: Panel parameters
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*
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* @ac_bias: AC Bias Pin Frequency
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* @ac_bias_intrpt: AC Bias Pin Transitions per Interrupt
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* @dma_burst_sz: DMA burst size
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* @bpp: Bits per pixel
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* @fdd: FIFO DMA Request Delay
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* @tft_alt_mode: TFT Alternative Signal Mapping (Only for active)
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* @invert_pxl_clk: Invert pixel clock
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* @sync_edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
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* @sync_ctrl: Horizontal and Vertical Sync: Control: 0=ignore
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* @raster_order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most
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* @fifo_th: DMA FIFO threshold
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*/
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struct tilcdc_panel_info {
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u32 ac_bias;
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u32 ac_bias_intrpt;
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u32 dma_burst_sz;
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u32 bpp;
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u32 fdd;
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bool tft_alt_mode;
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bool invert_pxl_clk;
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u32 sync_edge;
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u32 sync_ctrl;
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u32 raster_order;
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u32 fifo_th;
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};
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struct am335x_fb_priv {
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struct am335x_lcdhw *regs;
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struct tilcdc_panel_info panel;
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struct display_timing timing;
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};
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static int am335x_fb_remove(struct udevice *dev)
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{
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struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
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uc_plat->base -= 0x20;
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uc_plat->size += 0x20;
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return 0;
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}
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static int am335x_fb_probe(struct udevice *dev)
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{
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struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct am335x_fb_priv *priv = dev_get_priv(dev);
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struct am335x_lcdhw *regs = priv->regs;
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struct tilcdc_panel_info *panel = &priv->panel;
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struct display_timing *timing = &priv->timing;
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struct cm_dpll *const cmdpll = (struct cm_dpll *)CM_DPLL;
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u32 reg;
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/* Before relocation we don't need to do anything */
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if (!(gd->flags & GD_FLG_RELOC))
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return 0;
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am335x_fb_set_pixel_clk_rate(regs, timing->pixelclock.typ);
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/* clock source for LCDC from dispPLL M2 */
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writel(0, &cmdpll->clklcdcpixelclk);
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/* palette default entry */
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memset((void *)uc_plat->base, 0, 0x20);
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*(unsigned int *)uc_plat->base = 0x4000;
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/* point fb behind palette */
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uc_plat->base += 0x20;
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uc_plat->size -= 0x20;
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writel(LCDC_CLKC_ENABLE_CORECLKEN | LCDC_CLKC_ENABLE_LIDDCLKEN |
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LCDC_CLKC_ENABLE_DMACLKEN, ®s->clkc_enable);
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writel(0, ®s->raster_ctrl);
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reg = readl(®s->ctrl) & LCDC_CTRL_CLK_DIVISOR_MASK;
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reg |= LCDC_CTRL_RASTER_MODE;
|
|
writel(reg, ®s->ctrl);
|
|
|
|
writel(uc_plat->base, ®s->lcddma_fb0_base);
|
|
writel(uc_plat->base + FBSIZE(timing, panel),
|
|
®s->lcddma_fb0_ceiling);
|
|
writel(uc_plat->base, ®s->lcddma_fb1_base);
|
|
writel(uc_plat->base + FBSIZE(timing, panel),
|
|
®s->lcddma_fb1_ceiling);
|
|
|
|
reg = LCDC_DMA_CTRL_FIFO_TH(panel->fifo_th);
|
|
switch (panel->dma_burst_sz) {
|
|
case 1:
|
|
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_1);
|
|
break;
|
|
case 2:
|
|
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_2);
|
|
break;
|
|
case 4:
|
|
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_4);
|
|
break;
|
|
case 8:
|
|
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_8);
|
|
break;
|
|
case 16:
|
|
reg |= LCDC_DMA_CTRL_BURST_SIZE(LCDC_DMA_CTRL_BURST_16);
|
|
break;
|
|
}
|
|
|
|
writel(reg, ®s->lcddma_ctrl);
|
|
|
|
writel(LCDC_RASTER_TIMING_0_HORLSB(timing->hactive.typ) |
|
|
LCDC_RASTER_TIMING_0_HORMSB(timing->hactive.typ) |
|
|
LCDC_RASTER_TIMING_0_HFPLSB(timing->hfront_porch.typ) |
|
|
LCDC_RASTER_TIMING_0_HBPLSB(timing->hback_porch.typ) |
|
|
LCDC_RASTER_TIMING_0_HSWLSB(timing->hsync_len.typ),
|
|
®s->raster_timing0);
|
|
|
|
writel(LCDC_RASTER_TIMING_1_VBP(timing->vback_porch.typ) |
|
|
LCDC_RASTER_TIMING_1_VFP(timing->vfront_porch.typ) |
|
|
LCDC_RASTER_TIMING_1_VSW(timing->vsync_len.typ) |
|
|
LCDC_RASTER_TIMING_1_VERLSB(timing->vactive.typ),
|
|
®s->raster_timing1);
|
|
|
|
reg = LCDC_RASTER_TIMING_2_ACB(panel->ac_bias) |
|
|
LCDC_RASTER_TIMING_2_ACBI(panel->ac_bias_intrpt) |
|
|
LCDC_RASTER_TIMING_2_HSWMSB(timing->hsync_len.typ) |
|
|
LCDC_RASTER_TIMING_2_VERMSB(timing->vactive.typ) |
|
|
LCDC_RASTER_TIMING_2_HBPMSB(timing->hback_porch.typ) |
|
|
LCDC_RASTER_TIMING_2_HFPMSB(timing->hfront_porch.typ);
|
|
|
|
if (timing->flags & DISPLAY_FLAGS_VSYNC_LOW)
|
|
reg |= LCDC_RASTER_TIMING_2_VSYNC_INVERT;
|
|
|
|
if (timing->flags & DISPLAY_FLAGS_HSYNC_LOW)
|
|
reg |= LCDC_RASTER_TIMING_2_HSYNC_INVERT;
|
|
|
|
if (panel->invert_pxl_clk)
|
|
reg |= LCDC_RASTER_TIMING_2_PXCLK_INVERT;
|
|
|
|
if (panel->sync_edge)
|
|
reg |= LCDC_RASTER_TIMING_2_HSVS_RISEFALL;
|
|
|
|
if (panel->sync_ctrl)
|
|
reg |= LCDC_RASTER_TIMING_2_HSVS_CONTROL;
|
|
|
|
writel(reg, ®s->raster_timing2);
|
|
|
|
reg = LCDC_RASTER_CTRL_PALMODE_RAWDATA | LCDC_RASTER_CTRL_TFT_MODE |
|
|
LCDC_RASTER_CTRL_ENABLE | LCDC_RASTER_CTRL_REQDLY(panel->fdd);
|
|
|
|
if (panel->tft_alt_mode)
|
|
reg |= LCDC_RASTER_CTRL_TFT_ALT_ENABLE;
|
|
|
|
if (panel->bpp == 24)
|
|
reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE;
|
|
else if (panel->bpp == 32)
|
|
reg |= LCDC_RASTER_CTRL_TFT_24BPP_MODE |
|
|
LCDC_RASTER_CTRL_TFT_24BPP_UNPACK;
|
|
|
|
if (panel->raster_order)
|
|
reg |= LCDC_RASTER_CTRL_DATA_ORDER;
|
|
|
|
writel(reg, ®s->raster_ctrl);
|
|
|
|
uc_priv->xsize = timing->hactive.typ;
|
|
uc_priv->ysize = timing->vactive.typ;
|
|
uc_priv->bpix = log_2_n_round_up(panel->bpp);
|
|
return 0;
|
|
}
|
|
|
|
static int am335x_fb_of_to_plat(struct udevice *dev)
|
|
{
|
|
struct am335x_fb_priv *priv = dev_get_priv(dev);
|
|
struct tilcdc_panel_info *panel = &priv->panel;
|
|
struct display_timing *timing = &priv->timing;
|
|
ofnode node;
|
|
int err;
|
|
|
|
node = ofnode_by_compatible(ofnode_null(), "ti,am33xx-tilcdc");
|
|
if (!ofnode_valid(node)) {
|
|
dev_err(dev, "missing 'ti,am33xx-tilcdc' node\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
priv->regs = (struct am335x_lcdhw *)ofnode_get_addr(node);
|
|
dev_dbg(dev, "LCD: base address=0x%x\n", (unsigned int)priv->regs);
|
|
|
|
err = ofnode_decode_display_timing(dev_ofnode(dev), 0, timing);
|
|
if (err) {
|
|
dev_err(dev, "failed to get display timing\n");
|
|
return err;
|
|
}
|
|
|
|
if (timing->pixelclock.typ > (LCDC_FMAX / 2)) {
|
|
dev_err(dev, "invalid display clock-frequency: %d Hz\n",
|
|
timing->pixelclock.typ);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (timing->hactive.typ > LCD_MAX_WIDTH)
|
|
timing->hactive.typ = LCD_MAX_WIDTH;
|
|
|
|
if (timing->vactive.typ > LCD_MAX_HEIGHT)
|
|
timing->vactive.typ = LCD_MAX_HEIGHT;
|
|
|
|
node = ofnode_find_subnode(dev_ofnode(dev), "panel-info");
|
|
if (!ofnode_valid(node)) {
|
|
dev_err(dev, "missing 'panel-info' node\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
err |= ofnode_read_u32(node, "ac-bias", &panel->ac_bias);
|
|
err |= ofnode_read_u32(node, "ac-bias-intrpt", &panel->ac_bias_intrpt);
|
|
err |= ofnode_read_u32(node, "dma-burst-sz", &panel->dma_burst_sz);
|
|
err |= ofnode_read_u32(node, "bpp", &panel->bpp);
|
|
err |= ofnode_read_u32(node, "fdd", &panel->fdd);
|
|
err |= ofnode_read_u32(node, "sync-edge", &panel->sync_edge);
|
|
err |= ofnode_read_u32(node, "sync-ctrl", &panel->sync_ctrl);
|
|
err |= ofnode_read_u32(node, "raster-order", &panel->raster_order);
|
|
err |= ofnode_read_u32(node, "fifo-th", &panel->fifo_th);
|
|
if (err) {
|
|
dev_err(dev, "failed to get panel info\n");
|
|
return err;
|
|
}
|
|
|
|
switch (panel->bpp) {
|
|
case 16:
|
|
case 24:
|
|
case 32:
|
|
break;
|
|
default:
|
|
dev_err(dev, "invalid seting, bpp: %d\n", panel->bpp);
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (panel->dma_burst_sz) {
|
|
case 1:
|
|
case 2:
|
|
case 4:
|
|
case 8:
|
|
case 16:
|
|
break;
|
|
default:
|
|
dev_err(dev, "invalid setting, dma-burst-sz: %d\n",
|
|
panel->dma_burst_sz);
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* optional */
|
|
panel->tft_alt_mode = ofnode_read_bool(node, "tft-alt-mode");
|
|
panel->invert_pxl_clk = ofnode_read_bool(node, "invert-pxl-clk");
|
|
|
|
dev_dbg(dev, "LCD: %dx%d, bpp=%d, clk=%d Hz\n", timing->hactive.typ,
|
|
timing->vactive.typ, panel->bpp, timing->pixelclock.typ);
|
|
dev_dbg(dev, " hbp=%d, hfp=%d, hsw=%d\n", timing->hback_porch.typ,
|
|
timing->hfront_porch.typ, timing->hsync_len.typ);
|
|
dev_dbg(dev, " vbp=%d, vfp=%d, vsw=%d\n", timing->vback_porch.typ,
|
|
timing->vfront_porch.typ, timing->vsync_len.typ);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int am335x_fb_bind(struct udevice *dev)
|
|
{
|
|
struct video_uc_plat *uc_plat = dev_get_uclass_plat(dev);
|
|
|
|
uc_plat->size = ((LCD_MAX_WIDTH * LCD_MAX_HEIGHT *
|
|
(1 << LCD_MAX_LOG2_BPP)) >> 3) + 0x20;
|
|
|
|
dev_dbg(dev, "frame buffer size 0x%x\n", uc_plat->size);
|
|
return 0;
|
|
}
|
|
|
|
static const struct udevice_id am335x_fb_ids[] = {
|
|
{ .compatible = "ti,tilcdc,panel" },
|
|
{ }
|
|
};
|
|
|
|
U_BOOT_DRIVER(am335x_fb) = {
|
|
.name = "am335x_fb",
|
|
.id = UCLASS_VIDEO,
|
|
.of_match = am335x_fb_ids,
|
|
.bind = am335x_fb_bind,
|
|
.of_to_plat = am335x_fb_of_to_plat,
|
|
.probe = am335x_fb_probe,
|
|
.remove = am335x_fb_remove,
|
|
.priv_auto = sizeof(struct am335x_fb_priv),
|
|
};
|
|
|
|
#endif /* CONFIG_DM_VIDEO */
|