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306f527eff
It was found that the L2 cache timings that we had before could cause
freezes and hangs. We should make things more robust with better
timings. Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't take our kernel hacks).
This also provides a big cleanup of the L2 cache init code avoiding
some duplication. The way things used to work:
* low_power_start() was installed by the SPL (both at boot and resume
time) and left resident in iRAM for the kernel to use when bringing
up additional CPUs. It used configure_l2_ctlr() and
configure_l2_actlr() when it detected it was on an A15. This was
needed (despite the L2 cache registers being shared among all A15s)
because we might have been the first man in after the whole A15
cluster was shutdown.
* secondary_cores_configure() was called on at boot time and at resume
time. Strangely this called configure_l2_ctlr() but not
configure_l2_actlr() which was almost certainly wrong. Given that
we'll call both (see next bullet) later in the boot process it
didn't matter for normal boot, but I guess this is how L2 cache
settings got set on 5420/5800 (but not 5250?) at resume time.
* exynos5_set_l2cache_params() was called as part of cache enablement.
This should happen at boot time (normally in the SPL except for USB
boot where it happens in main U-Boot).
Note that the old code wasn't setting ECC/parity in the cache
enablement code but we happened to get it anyway because we'd call
secondary_cores_configure() at boot time. For resume time we'd get it
anyway when the 2nd A15 core came up.
Let's make this a whole lot simpler. Now we always set these
parameters in the same place for all boots and use the same code for
setting up secondary CPUs.
Intended net effects of this change (other than cleanup):
* Timings go from before:
data: 0 cycle setup, 3 cycles (0x2) latency
tag: 0 cycle setup, 3 cycles (0x2) latency
after:
data: 1 cycle setup, 4 cycles (0x3) latency
tag: 1 cycle setup, 4 cycles (0x3) latency
* L2ACTLR is properly initted on 5420/5800 in all cases.
One note is that we're still relying on luck to keep low_power_start()
working. The compiler is being nice and not storing anything on the
stack.
Another note is that on its own this patch won't help to fix cache
settings in an RW U-Boot update where we still have the RO SPL. The
plan for that is:
* Have RW U-Boot re-init the cache right before calling the kernel
(after it has turned the L2 cache off). This is why the functions
are in a header file instead of lowlevel_init.c.
* Have the kernel save the L2 cache settings of the boot CPU and apply
them to all other CPUs. We get a little lucky here because the old
code was using "|=" to modify the registers and all of the bits that
it's setting are also present in the new settings (!). That means
that when the 2nd CPU in the A15 cluster comes up it doesn't
actually mess up the settings of the 1st CPU in the A15 cluster. An
alternative option is to have the kernel write its own
low_power_start() code.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Akshay Saraswat <akshay.s@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
107 lines
2.7 KiB
C
107 lines
2.7 KiB
C
/*
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* Common APIs for EXYNOS based board
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*
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* Copyright (C) 2013 Samsung Electronics
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* Rajeshwari Shinde <rajeshwari.s@samsung.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/arch/system.h>
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#define DMC_OFFSET 0x10000
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/*
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* Memory initialization
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*
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* @param reset Reset PHY during initialization.
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*/
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void mem_ctrl_init(int reset);
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/* System Clock initialization */
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void system_clock_init(void);
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/*
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* Init subsystems according to the reset status
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*
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* @return 0 for a normal boot, non-zero for a resume
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*/
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int do_lowlevel_init(void);
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void sdelay(unsigned long);
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enum l2_cache_params {
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CACHE_DATA_RAM_LATENCY_2_CYCLES = (2 << 0),
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CACHE_DATA_RAM_LATENCY_3_CYCLES = (3 << 0),
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CACHE_DISABLE_CLEAN_EVICT = (1 << 3),
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CACHE_DATA_RAM_SETUP = (1 << 5),
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CACHE_TAG_RAM_LATENCY_2_CYCLES = (2 << 6),
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CACHE_TAG_RAM_LATENCY_3_CYCLES = (3 << 6),
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CACHE_ENABLE_HAZARD_DETECT = (1 << 7),
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CACHE_TAG_RAM_SETUP = (1 << 9),
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CACHE_ECC_AND_PARITY = (1 << 21),
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CACHE_ENABLE_FORCE_L2_LOGIC = (1 << 27)
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};
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#ifndef CONFIG_SYS_L2CACHE_OFF
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/*
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* Configure L2CTLR to get timings that keep us from hanging/crashing.
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*
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* Must be inline here since low_power_start() is called without a
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* stack (!).
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*/
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static inline void configure_l2_ctlr(void)
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{
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uint32_t val;
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mrc_l2_ctlr(val);
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val |= CACHE_TAG_RAM_SETUP |
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CACHE_DATA_RAM_SETUP |
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CACHE_TAG_RAM_LATENCY_2_CYCLES |
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CACHE_DATA_RAM_LATENCY_2_CYCLES;
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if (proid_is_exynos5420() || proid_is_exynos5800()) {
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val |= CACHE_ECC_AND_PARITY |
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CACHE_TAG_RAM_LATENCY_3_CYCLES |
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CACHE_DATA_RAM_LATENCY_3_CYCLES;
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}
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mcr_l2_ctlr(val);
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}
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/*
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* Configure L2ACTLR.
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*
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* Must be inline here since low_power_start() is called without a
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* stack (!).
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*/
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static inline void configure_l2_actlr(void)
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{
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uint32_t val;
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if (proid_is_exynos5420() || proid_is_exynos5800()) {
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mrc_l2_aux_ctlr(val);
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val |= CACHE_ENABLE_FORCE_L2_LOGIC |
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CACHE_DISABLE_CLEAN_EVICT;
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mcr_l2_aux_ctlr(val);
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}
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}
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#endif
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