mirror of
https://github.com/AsahiLinux/u-boot
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873e3ef90b
Based on Venice2, incorporates Stephen Warren's latest P2571 pinmux table. With Thierry Reding's 64-bit build fixes, this will build and and boot in 64-bit on my P2571 (when used with a 32-bit AVP loader). Signed-off-by: Tom Warren <twarren@nvidia.com>
85 lines
2.6 KiB
C
85 lines
2.6 KiB
C
/*
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* (C) Copyright 2013-2015
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* NVIDIA Corporation <www.nvidia.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch-tegra/tegra_i2c.h>
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#include "max77620_init.h"
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/* MAX77620-PMIC-specific early init code - get CPU rails up, etc */
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void tegra_i2c_ll_write_addr(uint addr, uint config)
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{
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struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
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writel(addr, ®->cmd_addr0);
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writel(config, ®->cnfg);
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}
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void tegra_i2c_ll_write_data(uint data, uint config)
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{
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struct i2c_ctlr *reg = (struct i2c_ctlr *)TEGRA_DVC_BASE;
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writel(data, ®->cmd_data1);
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writel(config, ®->cnfg);
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}
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void pmic_enable_cpu_vdd(void)
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{
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uint reg;
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debug("%s entry\n", __func__);
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/* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
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debug("%s: Setting GPIO5 to enable CPU regulator\n", __func__);
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/* B3=1=logic high,B2=dontcare,B1=0=output,B0=1=push-pull */
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reg = 0x0900 | MAX77620_GPIO5_REG;
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tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
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udelay(10 * 1000);
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/* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN */
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debug("%s: Setting GPIO1 to enable HDMI\n", __func__);
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reg = 0x0900 | MAX77620_GPIO1_REG;
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tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
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udelay(10 * 1000);
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/* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */
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reg = 0x1C00 | MAX77620_AME_GPIO;
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tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
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udelay(10 * 1000);
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/* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v */
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debug("%s: Set SD1 for LPDDR4, disable SD1RS, voltage to 1.125v\n",
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__func__);
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/* bit1=0, SD1 remote sense disabled */
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reg = 0x0400 | MAX77620_CNFG2SD_REG;
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tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
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udelay(10 * 1000);
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/* SD1 output = 1.125V */
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reg = 0x2A00 | MAX77620_SD1_REG;
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tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
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udelay(10 * 1000);
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debug("%s: Set LDO2 for VDDIO_SDMMC_AP power to 3.3V\n", __func__);
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/* 0xF2 for 3.3v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
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reg = 0xF200 | MAX77620_CNFG1_L2_REG;
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tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
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udelay(10 * 1000);
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debug("%s: Set LDO1 for USB3 phy power to 1.05V??\n", __func__);
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/* 0xCA for 105v, enabled: bit7:6 = 11 = enable, bit5:0 = voltage */
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reg = 0xCA00 | MAX77620_CNFG1_L1_REG;
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tegra_i2c_ll_write_addr(MAX77620_I2C_ADDR, 2);
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tegra_i2c_ll_write_data(reg, I2C_SEND_2_BYTES);
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udelay(10 * 1000);
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}
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