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https://github.com/AsahiLinux/u-boot
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b9a66b63b4
This GPIO controller device is used on UniPhier SoCs. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
147 lines
3.5 KiB
C
147 lines
3.5 KiB
C
/*
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* Copyright (C) 2016 Masahiro Yamada <yamada.masahiro@socionext.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dm/device.h>
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#include <mapmem.h>
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#include <linux/bitops.h>
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#include <linux/io.h>
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#include <asm/errno.h>
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#include <asm/gpio.h>
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#define UNIPHIER_GPIO_PORTS_PER_BANK 8
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#define UNIPHIER_GPIO_REG_DATA 0 /* data */
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#define UNIPHIER_GPIO_REG_DIR 4 /* direction (1:in, 0:out) */
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struct uniphier_gpio_priv {
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void __iomem *base;
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char bank_name[16];
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};
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static void uniphier_gpio_offset_write(struct udevice *dev, unsigned offset,
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unsigned reg, int value)
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{
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struct uniphier_gpio_priv *priv = dev_get_priv(dev);
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u32 tmp;
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tmp = readl(priv->base + reg);
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if (value)
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tmp |= BIT(offset);
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else
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tmp &= ~BIT(offset);
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writel(tmp, priv->base + reg);
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}
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static int uniphier_gpio_offset_read(struct udevice *dev, unsigned offset,
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unsigned reg)
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{
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struct uniphier_gpio_priv *priv = dev_get_priv(dev);
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return !!(readl(priv->base + reg) & BIT(offset));
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}
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static int uniphier_gpio_direction_input(struct udevice *dev, unsigned offset)
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{
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uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 1);
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return 0;
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}
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static int uniphier_gpio_direction_output(struct udevice *dev, unsigned offset,
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int value)
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{
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uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value);
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uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DIR, 0);
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return 0;
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}
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static int uniphier_gpio_get_value(struct udevice *dev, unsigned offset)
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{
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return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DATA);
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}
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static int uniphier_gpio_set_value(struct udevice *dev, unsigned offset,
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int value)
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{
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uniphier_gpio_offset_write(dev, offset, UNIPHIER_GPIO_REG_DATA, value);
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return 0;
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}
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static int uniphier_gpio_get_function(struct udevice *dev, unsigned offset)
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{
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return uniphier_gpio_offset_read(dev, offset, UNIPHIER_GPIO_REG_DIR) ?
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GPIOF_INPUT : GPIOF_OUTPUT;
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}
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static const struct dm_gpio_ops uniphier_gpio_ops = {
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.direction_input = uniphier_gpio_direction_input,
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.direction_output = uniphier_gpio_direction_output,
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.get_value = uniphier_gpio_get_value,
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.set_value = uniphier_gpio_set_value,
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.get_function = uniphier_gpio_get_function,
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};
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static int uniphier_gpio_probe(struct udevice *dev)
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{
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struct uniphier_gpio_priv *priv = dev_get_priv(dev);
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struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
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DECLARE_GLOBAL_DATA_PTR;
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fdt_addr_t addr;
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fdt_size_t size;
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unsigned int tmp;
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addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg",
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&size);
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if (addr == FDT_ADDR_T_NONE)
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return -EINVAL;
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priv->base = map_sysmem(addr, size);
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if (!priv->base)
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return -ENOMEM;
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uc_priv->gpio_count = UNIPHIER_GPIO_PORTS_PER_BANK;
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tmp = (addr & 0xfff);
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/* Unfortunately, there is a register hole at offset 0x90-0x9f. */
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if (tmp > 0x90)
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tmp -= 0x10;
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snprintf(priv->bank_name, sizeof(priv->bank_name) - 1,
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"port%d-", (tmp - 8) / 8);
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uc_priv->bank_name = priv->bank_name;
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return 0;
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}
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static int uniphier_gpio_remove(struct udevice *dev)
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{
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struct uniphier_gpio_priv *priv = dev_get_priv(dev);
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unmap_sysmem(priv->base);
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return 0;
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}
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/* .data = the number of GPIO banks */
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static const struct udevice_id uniphier_gpio_match[] = {
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{ .compatible = "socionext,uniphier-gpio" },
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(uniphier_gpio) = {
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.name = "uniphier_gpio",
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.id = UCLASS_GPIO,
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.of_match = uniphier_gpio_match,
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.probe = uniphier_gpio_probe,
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.remove = uniphier_gpio_remove,
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.priv_auto_alloc_size = sizeof(struct uniphier_gpio_priv),
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.ops = &uniphier_gpio_ops,
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};
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