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https://github.com/AsahiLinux/u-boot
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2b5b2be5e9
At this time I2C and responsible pin-mux is setup during PMIC initialziation within common.c, this is possible because today PMIC is always connected on I2C0. In Future this will be changed, PMIC isn't anymore connected to bus0 in call cases. So we do following: - rename enable_i2c_pin_mux0 to enable_i2c_pin_mux to be generic for enabling pin-mux on different or more busses. - move the call to i2c_pin_mux and i2c_init from common.c to the specific board.c Signed-off-by: Hannes Petermaier <hannes.petermaier@br-automation.com> Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
248 lines
10 KiB
C
248 lines
10 KiB
C
/*
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* mux.c
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*
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* Pinmux Setting for B&R LEIT Board(s)
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*
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* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
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* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/mux.h>
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#include <asm/io.h>
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#include <i2c.h>
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static struct module_pin_mux uart0_pin_mux[] = {
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/* UART0_CTS */
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{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART0_RXD */
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{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART0_TXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
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{-1},
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};
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static struct module_pin_mux uart1_pin_mux[] = {
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/* UART0_RXD */
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{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* UART0_TXD */
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{OFFSET(uart1_txd), (MODE(0) | PULLUDEN)},
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{-1},
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};
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#ifdef CONFIG_MMC
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static struct module_pin_mux mmc1_pin_mux[] = {
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{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT7 */
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{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT6 */
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{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT5 */
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{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT4 */
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{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT2 */
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{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT1 */
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{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)}, /* MMC1_DAT0 */
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{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CLK */
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{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)}, /* MMC1_CMD */
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{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)}, /* MMC1_WP */
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{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
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{-1},
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};
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#endif
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static struct module_pin_mux i2c0_pin_mux[] = {
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/* I2C_DATA */
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{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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/* I2C_SCLK */
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{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
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{-1},
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};
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static struct module_pin_mux spi0_pin_mux[] = {
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/* SPI0_SCLK */
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{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
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/* SPI0_D0 */
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{OFFSET(spi0_d0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
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/* SPI0_D1 */
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{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
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/* SPI0_CS0 */
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{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
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{-1},
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};
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static struct module_pin_mux mii1_pin_mux[] = {
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{OFFSET(mii1_crs), MODE(0) | RXACTIVE}, /* MII1_CRS */
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{OFFSET(mii1_col), MODE(0) | RXACTIVE}, /* MII1_COL */
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{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE}, /* MII1_RXERR */
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{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
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{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE}, /* MII1_RXDV */
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{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
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{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
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{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
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{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
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{OFFSET(mii1_txclk), MODE(0) | RXACTIVE}, /* MII1_TXCLK */
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{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE}, /* MII1_RXCLK */
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{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE}, /* MII1_RXD3 */
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{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE}, /* MII1_RXD2 */
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{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE}, /* MII1_RXD1 */
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{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE}, /* MII1_RXD0 */
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{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
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{OFFSET(mdio_clk), MODE(0) | PULLUP_EN}, /* MDIO_CLK */
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{-1},
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};
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static struct module_pin_mux mii2_pin_mux[] = {
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{OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
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{OFFSET(gpmc_a1), MODE(1) | RXACTIVE}, /* MII2_RXDV */
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{OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
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{OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
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{OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
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{OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */
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{OFFSET(gpmc_a6), MODE(1) | RXACTIVE}, /* MII2_TXCLK */
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{OFFSET(gpmc_a7), MODE(1) | RXACTIVE}, /* MII2_RXCLK */
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{OFFSET(gpmc_a8), MODE(1) | RXACTIVE}, /* MII2_RXD3 */
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{OFFSET(gpmc_a9), MODE(1) | RXACTIVE}, /* MII2_RXD2 */
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{OFFSET(gpmc_a10), MODE(1) | RXACTIVE}, /* MII2_RXD1 */
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{OFFSET(gpmc_a11), MODE(1) | RXACTIVE}, /* MII2_RXD0 */
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{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
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{OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
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/*
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* MII2_CRS is shared with
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* NAND_WAIT0
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*/
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{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
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{-1},
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};
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#ifdef CONFIG_NAND
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static struct module_pin_mux nand_pin_mux[] = {
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{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD0 */
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{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD1 */
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{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD2 */
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{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD3 */
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{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD4 */
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{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD5 */
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{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD6 */
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{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* NAND AD7 */
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{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)}, /* NAND WAIT */
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{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)}, /* NAND_WPN */
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{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)}, /* NAND_CS0 */
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{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)}, /* NAND_ADV_ALE */
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{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)}, /* NAND_OE */
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{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)}, /* NAND_WEN */
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{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)}, /* NAND_BE_CLE */
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{-1},
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};
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#endif
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static struct module_pin_mux gpIOs[] = {
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/* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
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{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
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{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
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/* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3 */
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{OFFSET(mmc0_dat2), (MODE(3) | PULLUDEN | RXACTIVE)},
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/* GPIO2_28 (MMC0_DAT1) - MII_nNAND */
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{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
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/* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
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{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
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/* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
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{OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
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{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
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{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
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{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
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{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* GPIO2_0 (GPMC_nCS3) - DCOK */
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{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
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/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
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{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
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/*
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* GPIO0_7 (PWW0 OUT)
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* DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
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*/
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{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
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/* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
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{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
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/* GPIO0_20 (DMA_INTR1) - REP-Switch */
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{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
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/* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
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{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
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/* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
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{OFFSET(mcasp0_fsx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
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/* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
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{OFFSET(mcasp0_axr0), (MODE(7) | PULLUDDIS) },
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/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
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{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },
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#ifndef CONFIG_NAND
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/* GPIO2_3 - NAND_OE */
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{OFFSET(gpmc_oen_ren), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
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/* GPIO2_4 - NAND_WEN */
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{OFFSET(gpmc_wen), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
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/* GPIO2_5 - NAND_BE_CLE */
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{OFFSET(gpmc_be0n_cle), (MODE(7) | PULLDOWN_EN | RXACTIVE)},
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#endif
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{-1},
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};
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static struct module_pin_mux lcd_pin_mux[] = {
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{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)}, /* LCD-Data(0) */
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{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)}, /* LCD-Data(1) */
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{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)}, /* LCD-Data(2) */
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{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)}, /* LCD-Data(3) */
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{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)}, /* LCD-Data(4) */
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{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)}, /* LCD-Data(5) */
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{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)}, /* LCD-Data(6) */
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{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)}, /* LCD-Data(7) */
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{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)}, /* LCD-Data(8) */
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{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)}, /* LCD-Data(9) */
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{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)}, /* LCD-Data(10) */
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{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)}, /* LCD-Data(11) */
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{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)}, /* LCD-Data(12) */
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{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)}, /* LCD-Data(13) */
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{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)}, /* LCD-Data(14) */
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{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)}, /* LCD-Data(15) */
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{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)}, /* LCD-Data(16) */
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{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)}, /* LCD-Data(17) */
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{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)}, /* LCD-Data(18) */
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{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)}, /* LCD-Data(19) */
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{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)}, /* LCD-Data(20) */
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{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)}, /* LCD-Data(21) */
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{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)}, /* LCD-Data(22) */
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{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)}, /* LCD-Data(23) */
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{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)}, /* LCD-VSync */
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{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)}, /* LCD-HSync */
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{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
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{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)}, /* LCD-CLK */
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{-1},
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};
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void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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}
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void enable_i2c_pin_mux(void)
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{
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configure_module_pin_mux(i2c0_pin_mux);
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}
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void enable_board_pin_mux(void)
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{
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configure_module_pin_mux(i2c0_pin_mux);
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configure_module_pin_mux(mii1_pin_mux);
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configure_module_pin_mux(mii2_pin_mux);
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#ifdef CONFIG_NAND
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configure_module_pin_mux(nand_pin_mux);
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#elif defined(CONFIG_MMC)
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configure_module_pin_mux(mmc1_pin_mux);
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#endif
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configure_module_pin_mux(spi0_pin_mux);
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configure_module_pin_mux(lcd_pin_mux);
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configure_module_pin_mux(uart1_pin_mux);
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configure_module_pin_mux(gpIOs);
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}
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