mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-22 19:23:07 +00:00
a4fc6ee9e7
The reset_cpu() implementation is basically the same across Gen3 SoCs and identical across Gen4 SoCs. Introduce weak default for reset_cpu(), so that it does not have to be duplicated in every board file again. There is a slight difference for CA53 only systems, like E3 and D3, which now check MIDR for CPU ID first just like the other systems, but this is OK since the MIDR always returns CA53 core type and the correct reset register is written. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
103 lines
2.1 KiB
C
103 lines
2.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board/renesas/falcon/falcon.c
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* This file is Falcon board support.
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*
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* Copyright (C) 2020 Renesas Electronics Corp.
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*/
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#include <common.h>
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#include <asm/arch/rmobile.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/mach-types.h>
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#include <asm/processor.h>
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#include <linux/errno.h>
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#include <asm/system.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CPGWPR 0xE6150000
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#define CPGWPCR 0xE6150004
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#define EXTAL_CLK 16666600u
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#define CNTCR_BASE 0xE6080000
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#define CNTFID0 (CNTCR_BASE + 0x020)
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#define CNTCR_EN BIT(0)
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static void init_generic_timer(void)
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{
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u32 freq;
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/* Set frequency data in CNTFID0 */
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freq = EXTAL_CLK;
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/* Update memory mapped and register based freqency */
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asm volatile ("msr cntfrq_el0, %0" :: "r" (freq));
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writel(freq, CNTFID0);
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/* Enable counter */
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setbits_le32(CNTCR_BASE, CNTCR_EN);
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}
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/* Distributor Registers */
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#define GICD_BASE 0xF1000000
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/* ReDistributor Registers for Control and Physical LPIs */
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#define GICR_LPI_BASE 0xF1060000
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#define GICR_WAKER 0x0014
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#define GICR_PWRR 0x0024
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#define GICR_LPI_WAKER (GICR_LPI_BASE + GICR_WAKER)
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#define GICR_LPI_PWRR (GICR_LPI_BASE + GICR_PWRR)
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/* ReDistributor Registers for SGIs and PPIs */
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#define GICR_SGI_BASE 0xF1070000
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#define GICR_IGROUPR0 0x0080
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static void init_gic_v3(void)
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{
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/* GIC v3 power on */
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writel(0x00000002, (GICR_LPI_PWRR));
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/* Wait till the WAKER_CA_BIT changes to 0 */
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writel(readl(GICR_LPI_WAKER) & ~0x00000002, (GICR_LPI_WAKER));
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while (readl(GICR_LPI_WAKER) & 0x00000004)
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;
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writel(0xffffffff, GICR_SGI_BASE + GICR_IGROUPR0);
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}
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void s_init(void)
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{
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if (current_el() == 3)
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init_generic_timer();
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}
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int board_early_init_f(void)
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{
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/* Unlock CPG access */
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writel(0x5A5AFFFF, CPGWPR);
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writel(0xA5A50000, CPGWPCR);
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return 0;
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}
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#define RST_BASE 0xE6160000 /* Domain0 */
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#define RST_WDTRSTCR (RST_BASE + 0x10)
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#define RST_RWDT 0xA55A8002
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int board_init(void)
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{
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/* address of boot parameters */
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gd->bd->bi_boot_params = CONFIG_TEXT_BASE + 0x50000;
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if (current_el() == 3) {
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init_gic_v3();
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/* Enable RWDT reset */
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writel(RST_RWDT, RST_WDTRSTCR);
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}
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return 0;
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}
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