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u-boot/board/freescale/t102xrdb/README
Pali Rohár d8fa0a7668
Makefile: Build final mpc85xx non-SPL image in standard file u-boot.bin 
Currently Makefile produces final mpc85xx image when SPL is not used in
custom file u-boot-with-dtb.bin. It is quite confusing name as build
process produce also intermediate file standard file u-boot-dtb.bin (which
is just intermediate and not bootable). Other platforms use u-boot.bin
(UBOOT_BIN) as standard name for final bootable raw image.

So change Makefile rules and binman to produce final bootable file for
mpc85xx also into file u-boot.bin. There is just need for mpc85xx to not
define default rule for u-boot.bin then instruct binman (via DTS file) to
store final image into u-boot.bin (instead of u-boot-with-dtb.bin) and
finally rename target u-boot-with-dtb.bin to u-boot.bin.

With this change are also removed custom Makefile hacks for mpc85xx that it
produced non-standard output file. And also updated documentation.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Signed-off-by: Marek Behún <kabel@kernel.org>
2022-09-16 17:39:41 +02:00

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T1024 SoC Overview
------------------
The T1024/T1023 dual core and T1014/T1013 single core QorIQ communication processor
combines two or one 64-bit Power Architecture e5500 core respectively with high
performance datapath acceleration logic, and network peripheral bus interfaces
required for networking and telecommunications. This processor can be used in
applications such as enterprise WLAN access points, routers, switches, firewall
and other packet processing intensive small enterprise and branch office appliances,
and general-purpose embedded computing. Its high level of integration offers
significant performance benefits and greatly helps to simplify board design.
The T1024 SoC includes the following function and features:
- two e5500 cores, each with a private 256 KB L2 cache
- Up to 1.4 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
- Three levels of instructions: User, supervisor, and hypervisor
- Independent boot and reset
- Secure boot capability
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- CoreNet coherency manager supporting coherent and noncoherent transactions
with prioritization and bandwidth allocation amongst CoreNet endpoints
- 150 Gbps coherent read bandwidth
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion management
- Cryptography Acceleration (SEC 5.x)
- IEEE 1588 support
- Hardware buffer management for buffer allocation and deallocation
- MACSEC on DPAA-based Ethernet ports
- Ethernet interfaces
- Four 1 Gbps Ethernet controllers
- Parallel Ethernet interfaces
- Two RGMII interfaces
- High speed peripheral interfaces
- Three PCI Express 2.0 controllers/ports running at up to 5 GHz
- One SATA controller supporting 1.5 and 3.0 Gb/s operation
- One QSGMII interface
- Four SGMII interface supporting 1000 Mbps
- Three SGMII interfaces supporting up to 2500 Mbps
- 10GBase-R or 10Base-KR interface
- Additional peripheral interfaces
- Two USB 2.0 controllers with integrated PHY
- SD/eSDHC/eMMC
- eSPI controller
- Four I2C controllers
- Four UARTs
- Four GPIO controllers
- Integrated flash controller (IFC)
- LCD interface (DIU) with 12 bit dual data rate
- Multicore programmable interrupt controller (PIC)
- Two 8-channel DMA engines
- Single source clocking implementation
- Deep Sleep power implementaion (wakeup from GPIO/Timer/Ethernet/USB)
- QUICC Engine block
- 32-bit RISC controller for flexible support of the communications peripherals
- Serial DMA channel for receive and transmit on all serial channels
- Two universal communication controllers, supporting TDM, HDLC, and UART
T1023 Personality
------------------
T1023 is a reduced personality of T1024 without QUICC Engine, DIU, and
unavailable deep sleep. Rest of the blocks are almost same as T1024.
Differences between T1024 and T1023
Feature T1024 T1023
QUICC Engine: yes no
DIU: yes no
Deep Sleep: yes no
I2C controller: 4 3
DDR: 64-bit 32-bit
IFC: 32-bit 28-bit
Package: 23x23 19x19
T1024RDB board Overview
-----------------------
- Ethernet
- Two on-board 10M/100M/1G bps RGMII ethernet ports
- One on-board 10G bps Base-T port.
- DDR Memory
- Supports 64-bit 4GB DDR3L DIMM
- PCIe
- One on-board PCIe slot.
- Two on-board PCIe Mini-PCIe connectors.
- IFC/Local Bus
- NOR: 128MB 16-bit NOR Flash
- NAND: 1GB 8-bit NAND flash
- CPLD: for system controlling with programable header on-board
- USB
- Supports two USB 2.0 ports with integrated PHYs
- Two type A ports with 5V@1.5A per port.
- SDHC
- one SD connector supporting 1.8V/3.3V via J53.
- SPI
- On-board 64MB SPI flash
- Other
- Two Serial ports
- Four I2C ports
T1023RDB board Overview
-----------------------
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
- one 1G RGMII port on-board(RTL8211FS PHY)
- one 1G SGMII port on-board(RTL8211FS PHY)
- one 2.5G SGMII port on-board(AQR105 PHY)
- PCIe: Two Mini-PCIe connectors on-board.
- SerDes: 4 lanes up to 10.3125GHz
- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
- USB: one Type-A USB 2.0 port with internal PHY
- eSDHC: support SD/MMC and eMMC card
- 256Kbit M24256 I2C EEPROM
- RTC: Real-time clock DS1339U on I2C bus
- UART: one serial port on-board with RJ45 connector
- Debugging: JTAG/COP for T1023 debugging
Memory map on T1024RDB
----------------------
Start Address End Address Description Size
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
0xC_2000_0000 0xC_2FFF_FFFF PCI Express 3 Mem Space 256MB
0xC_1000_0000 0xC_1FFF_FFFF PCI Express 2 Mem Space 256MB
0xC_0000_0000 0xC_0FFF_FFFF PCI Express 1 Mem Space 256MB
0x0_0000_0000 0x0_ffff_ffff DDR 4GB
128MB NOR Flash Memory Layout
-----------------------------
Start Address End Address Definition Max size
0xEFF40000 0xEFFFFFFF U-Boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF U-Boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB
0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB
0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB
0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB
0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB
0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB
0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
0xEBF40000 0xEBFFFFFF U-Boot (alt bank) 768KB
0xEBF20000 0xEBF3FFFF U-Boot env (alt bank) 128KB
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB
0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB
0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB
0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB
0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB
0xE8000000 0xE801FFFF RCW (current bank) 128KB
T1024/T1023 Clock frequency
---------------------------
BIN Core DDR Platform FMan
Bin1: 1400MHz 1600MT/s 400MHz 700MHz
Bin2: 1200MHz 1600MT/s 400MHz 600MHz
Bin3: 1000MHz 1600MT/s 400MHz 500MHz
Software configurations and board settings
------------------------------------------
1. NOR boot:
a. build NOR boot image
$ make T1024RDB_defconfig
$ make
b. program u-boot.bin image to NOR flash
=> tftp 1000000 u-boot.bin
=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
on T1024RDB:
set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
on T1023RDB:
set SW1[1:8] = '00010111', SW2[1] = '1', SW3[4] = '0' for NOR boot
Switching between default bank0 and alternate bank4 on NOR flash
To change boot source to vbank4:
on T1024RDB:
via software: run command 'cpld reset altbank' in U-Boot.
via DIP-switch: set SW3[5:7] = '100'
on T1023RDB:
via software: run command 'switch bank4' in U-Boot.
via DIP-switch: set SW3[5:7] = '100'
To change boot source to vbank0:
on T1024RDB:
via software: run command 'cpld reset' in U-Boot.
via DIP-Switch: set SW3[5:7] = '000'
on T1023RDB:
via software: run command 'switch bank0' in U-Boot.
via DIP-switch: set SW3[5:7] = '000'
2. NAND Boot:
a. build PBL image for NAND boot
$ make T1024RDB_NAND_defconfig
$ make
b. program u-boot-with-spl-pbl.bin to NAND flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> nand erase 0 $filesize
=> nand write 1000000 0 $filesize
set SW1[1:8] = '10000010', SW2[1] = '1', SW3[4] = '1' for NAND boot
3. SPI Boot:
a. build PBL image for SPI boot
$ make T1024RDB_SPIFLASH_defconfig
$ make
b. program u-boot-with-spl-pbl.bin to SPI flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> sf probe 0
=> sf erase 0 100000
=> sf write 1000000 0 $filesize
=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
=> sf erase 100000 100000
=> sf write 1000000 110000 20000
set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
4. SD Boot:
a. build PBL image for SD boot
$ make T1024RDB_SDCARD_defconfig
$ make
b. program u-boot-with-spl-pbl.bin to SD/MMC card
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> mmc write 1000000 8 0x7f0
=> tftp 1000000 fsl_fman_ucode_t1024_xx.bin
=> mmc write 1000000 0x820 80
set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
SW3[3] = '1' for SD card(or 'switch sd' by software)
SW3[3] = '0' for eMMC (or 'switch emmc' by software)
device tree support and how to enable it for different configs
--------------------------------------------------------------
device tree support is available for t1024rdb for below mentioned boot,
1. nor boot
2. nand boot
3. sd boot
4. spiflash boot
to enable device tree support for other boot, below configs need to be
enabled in relative defconfig file,
1. config_default_device_tree="t1024rdb" (change default device tree name if required)
2. config_of_control
3. config_mpc85xx_have_reset_vector if reset vector is located at
config_reset_vector_address - 0xffc
if device tree support is enabled in defconfig,
1. use 'u-boot.bin' for nor boot.
2. use 'u-boot-with-spl-pbl.bin' for other boot.
2-stage NAND/SPI/SD boot loader
-------------------------------
PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
SPL further initializes DDR using SPD and environment variables
and copy U-Boot(768 KB) from NAND/SPI/SD device to DDR.
Finally SPL transers control to U-Boot for futher booting.
SPL has following features:
- Executes within 256K
- No relocation required
Run time view of SPL framework
-------------------------------------------------
|Area | Address |
-------------------------------------------------
|SecureBoot header | 0xFFFC0000 (32KB) |
-------------------------------------------------
|GD, BD | 0xFFFC8000 (4KB) |
-------------------------------------------------
|ENV | 0xFFFC9000 (8KB) |
-------------------------------------------------
|HEAP | 0xFFFCB000 (30KB) |
-------------------------------------------------
|STACK | 0xFFFD8000 (22KB) |
-------------------------------------------------
|U-Boot SPL | 0xFFFD8000 (160KB) |
-------------------------------------------------
NAND Flash memory Map on T1024RDB
-------------------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF U-Boot 1MB(2 block)
0x100000 0x17FFFF U-Boot env 512KB(1 block)
0x180000 0x1FFFFF FMAN Ucode 512KB(1 block)
0x200000 0x27FFFF QE Firmware 512KB(1 block)
NAND Flash memory Map on T1023RDB
----------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF U-Boot 1MB
0x100000 0x15FFFF U-Boot env 8KB
0x160000 0x17FFFF FMAN Ucode 128KB
SD Card memory Map on T102xRDB
----------------------------------------------------
Block #blocks Definition Size
0x008 2048 U-Boot img 1MB
0x800 0016 U-Boot env 8KB
0x820 0256 FMAN Ucode 128KB
0x920 0256 QE Firmware 128KB(only T1024RDB)
64MB SPI Flash memory Map on T102xRDB
----------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF U-Boot img 1MB
0x100000 0x101FFF U-Boot env 8KB
0x110000 0x12FFFF FMAN Ucode 128KB
0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB)
0x300000 0x3FFFFF device tree 128KB
0x400000 0x9FFFFF Linux kernel 6MB
0xa00000 0x3FFFFFF rootfs 54MB
For more details, please refer to T1024RDB/T1023RDB User Guide
and Freescale QorIQ SDK Infocenter document.
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