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1c382ead7a
Based on http://processors.wiki.ti.com/index.php/AM335x_EMIF_Configuration_tips we need to re-work our sequence in config_sdram slightly to match what the TRM describes as the correct sequence. In our current (incorrect) sequence some edge cases may fail to initalize correctly. Signed-off-by: Tom Rini <trini@ti.com>
125 lines
3.8 KiB
C
125 lines
3.8 KiB
C
/*
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* DDR Configuration for AM33xx devices.
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*
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* Copyright (C) 2011 Texas Instruments Incorporated -
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http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed .as is. WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <asm/arch/cpu.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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/**
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* Base address for EMIF instances
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*/
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static struct emif_reg_struct *emif_reg = {
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(struct emif_reg_struct *)EMIF4_0_CFG_BASE};
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/**
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* Base address for DDR instance
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*/
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static struct ddr_regs *ddr_reg[2] = {
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(struct ddr_regs *)DDR_PHY_BASE_ADDR,
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(struct ddr_regs *)DDR_PHY_BASE_ADDR2};
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/**
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* Base address for ddr io control instances
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*/
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static struct ddr_cmdtctrl *ioctrl_reg = {
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(struct ddr_cmdtctrl *)DDR_CONTROL_BASE_ADDR};
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/**
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* Configure SDRAM
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*/
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void config_sdram(const struct emif_regs *regs)
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{
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if (regs->zq_config) {
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/*
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* A value of 0x2800 for the REF CTRL will give us
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* about 570us for a delay, which will be long enough
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* to configure things.
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*/
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writel(0x2800, &emif_reg->emif_sdram_ref_ctrl);
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writel(regs->zq_config, &emif_reg->emif_zq_config);
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writel(regs->sdram_config, &cstat->secure_emif_sdram_config);
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}
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writel(regs->sdram_config, &emif_reg->emif_sdram_config);
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writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl);
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writel(regs->ref_ctrl, &emif_reg->emif_sdram_ref_ctrl_shdw);
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}
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/**
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* Set SDRAM timings
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*/
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void set_sdram_timings(const struct emif_regs *regs)
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{
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writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1);
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writel(regs->sdram_tim1, &emif_reg->emif_sdram_tim_1_shdw);
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writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2);
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writel(regs->sdram_tim2, &emif_reg->emif_sdram_tim_2_shdw);
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writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3);
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writel(regs->sdram_tim3, &emif_reg->emif_sdram_tim_3_shdw);
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}
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/**
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* Configure DDR PHY
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*/
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void config_ddr_phy(const struct emif_regs *regs)
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{
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writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1);
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writel(regs->emif_ddr_phy_ctlr_1, &emif_reg->emif_ddr_phy_ctrl_1_shdw);
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}
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/**
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* Configure DDR CMD control registers
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*/
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void config_cmd_ctrl(const struct cmd_control *cmd)
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{
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writel(cmd->cmd0csratio, &ddr_reg[0]->cm0csratio);
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writel(cmd->cmd0dldiff, &ddr_reg[0]->cm0dldiff);
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writel(cmd->cmd0iclkout, &ddr_reg[0]->cm0iclkout);
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writel(cmd->cmd1csratio, &ddr_reg[0]->cm1csratio);
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writel(cmd->cmd1dldiff, &ddr_reg[0]->cm1dldiff);
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writel(cmd->cmd1iclkout, &ddr_reg[0]->cm1iclkout);
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writel(cmd->cmd2csratio, &ddr_reg[0]->cm2csratio);
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writel(cmd->cmd2dldiff, &ddr_reg[0]->cm2dldiff);
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writel(cmd->cmd2iclkout, &ddr_reg[0]->cm2iclkout);
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}
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/**
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* Configure DDR DATA registers
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*/
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void config_ddr_data(int macrono, const struct ddr_data *data)
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{
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writel(data->datardsratio0, &ddr_reg[macrono]->dt0rdsratio0);
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writel(data->datawdsratio0, &ddr_reg[macrono]->dt0wdsratio0);
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writel(data->datawiratio0, &ddr_reg[macrono]->dt0wiratio0);
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writel(data->datagiratio0, &ddr_reg[macrono]->dt0giratio0);
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writel(data->datafwsratio0, &ddr_reg[macrono]->dt0fwsratio0);
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writel(data->datawrsratio0, &ddr_reg[macrono]->dt0wrsratio0);
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writel(data->datauserank0delay, &ddr_reg[macrono]->dt0rdelays0);
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writel(data->datadldiff0, &ddr_reg[macrono]->dt0dldiff0);
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}
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void config_io_ctrl(unsigned long val)
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{
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writel(val, &ioctrl_reg->cm0ioctl);
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writel(val, &ioctrl_reg->cm1ioctl);
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writel(val, &ioctrl_reg->cm2ioctl);
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writel(val, &ioctrl_reg->dt0ioctl);
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writel(val, &ioctrl_reg->dt1ioctl);
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}
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