mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-11 22:03:15 +00:00
21f11c7b49
The reset procedure works on watchdog timer while before it was modifying TIMER_1 registers. Tested on DM365. Signed-off-by: Davide Bonfanti <davide.bonfanti@bticino.it>
33 lines
991 B
C
33 lines
991 B
C
/*
|
|
* Processor reset using WDT.
|
|
*
|
|
* Copyright (C) 2012 Dmitry Bondar <bond@inmys.ru>
|
|
* Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
|
|
*
|
|
* This file is released under the terms of GPL v2 and any later version.
|
|
* See the file COPYING in the root directory of the source tree for details.
|
|
*/
|
|
|
|
#include <common.h>
|
|
#include <asm/io.h>
|
|
#include <asm/arch/timer_defs.h>
|
|
#include <asm/arch/hardware.h>
|
|
|
|
void reset_cpu(unsigned long a)
|
|
{
|
|
struct davinci_timer *const wdttimer =
|
|
(struct davinci_timer *)DAVINCI_WDOG_BASE;
|
|
writel(0x08, &wdttimer->tgcr);
|
|
writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr);
|
|
writel(0, &wdttimer->tim12);
|
|
writel(0, &wdttimer->tim34);
|
|
writel(0, &wdttimer->prd12);
|
|
writel(0, &wdttimer->prd34);
|
|
writel(readl(&wdttimer->tcr) | 0x40, &wdttimer->tcr);
|
|
writel(readl(&wdttimer->wdtcr) | 0x4000, &wdttimer->wdtcr);
|
|
writel(0xa5c64000, &wdttimer->wdtcr);
|
|
writel(0xda7e4000, &wdttimer->wdtcr);
|
|
writel(0x4000, &wdttimer->wdtcr);
|
|
while (1)
|
|
/*nothing*/;
|
|
}
|